emifs.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 2001, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Description    	: EMIFS configuration functions

   Author         	: Pradosh K Puthanpurayil

===============================================================================
*/

//#include "mem.h"
//#include "mif.h"
//#include "flashintel.h"
//#include "result.h"
#include "emiff_emifs_wt.h"
#include "emifs.h"


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigNCs0Reg
//
// DESCRIPTION  : For programming the CS0 Configuration register
//		  field bits 
//                                       
// PARAMETERS   : BTWST, MAD, FL, BW, RDMODE, PGWST_WELEN, WRWST, RDWST and 
//		  FCLKDIV.
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigNCs0Reg (	UWORD8 BTWST,
				UWORD8 MAD,
				UWORD8 FL,
				UWORD8 BW,
				UWORD8 RDMODE,
				UWORD8 PGWST_WELEN,
				UWORD8 WRWST,
				UWORD8 RDWST,
				UWORD8 FCLKDIV)
{
  UWORD32 tmp;

  /* Read the nCS0 config register */
  tmp = *(UWORD32*)EMIFS_nCS0_CONFIG_REG;

  /* Assign the RDWST value */
  tmp &= ~EMIFS_RD_WAIT_nCS0_MSK;
  tmp |= (RDWST << EMIFS_RD_WAIT_nCS0_BITPOS);

  /* Assign the RDMODE value */
  tmp &= ~EMIFS_RD_MODE_SEL_nCS0_MSK;
  tmp |= (RDMODE << EMIFS_RD_MODE_SEL_nCS0_BITPOS);

  /* Assign the WRWST value */
  tmp &= ~EMIFS_WR_WAIT_nCS0_MSK;
  tmp |= (WRWST << EMIFS_WR_WAIT_nCS0_BITPOS);

  /* Assign the PGWST/WELEN value */
  tmp &= ~EMIFS_PGWST_WELEN_nCS0_MSK;
  tmp |= (PGWST_WELEN << EMIFS_PGWST_WELEN_nCS0_BITPOS);

  /* Assign the BW value */
  tmp &= ~EMIFS_BUS_WIDTH_nCS0_MSK;
  tmp |= (BW << EMIFS_BUS_WIDTH_nCS0_BITPOS);

  /* Assign the Flash Intel value */
  tmp &= ~EMIFS_INTEL_FLASH_nCS0_MSK;
  tmp |= (FL << EMIFS_INTEL_FLASH_nCS0_BITPOS);

  /* Assign the Multiplexed Address/Data value */
  tmp &= ~EMIFS_MAD_nCS0_MSK;
  tmp |= (MAD << EMIFS_MAD_nCS0_BITPOS);

  /* Assign the BTWST value */
  tmp &= ~EMIFS_BT_WAIT_nCS0_MSK;
  tmp |= (BTWST << EMIFS_BT_WAIT_nCS0_BITPOS);

  /* Assign the FCLKDIV value */
  tmp &= ~EMIFS_FCLKDIV_nCS0_MSK;
  tmp |= (FCLKDIV << EMIFS_FCLKDIV_nCS0_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS0_CONFIG_REG = tmp;
}

//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigNCs1Reg
//
// DESCRIPTION  : For programming the CS1 Configuration register
//		  field bits 
//                                       
// PARAMETERS   : BTWST, MAD, FL, BW, RDMODE, PGWST_WELEN, WRWST, RDWST and 
//		  FCLKDIV.
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigNCs1Reg (	UWORD8 BTWST,
				UWORD8 MAD,
				UWORD8 FL,
				UWORD8 BW,
				UWORD8 RDMODE,
				UWORD8 PGWST_WELEN,
				UWORD8 WRWST,
				UWORD8 RDWST,
				UWORD8 FCLKDIV)
{
  UWORD32 tmp;

  /* Read the nCS1 config register */
  tmp = *(UWORD32*)EMIFS_nCS1_CONFIG_REG;

  /* Assign the RDWST value */
  tmp &= ~EMIFS_RD_WAIT_nCS1_MSK;
  tmp |= (RDWST << EMIFS_RD_WAIT_nCS1_BITPOS);

  /* Assign the RDMODE value */
  tmp &= ~EMIFS_RD_MODE_SEL_nCS1_MSK;
  tmp |= (RDMODE << EMIFS_RD_MODE_SEL_nCS1_BITPOS);

  /* Assign the WRWST value */
  tmp &= ~EMIFS_WR_WAIT_nCS1_MSK;
  tmp |= (WRWST << EMIFS_WR_WAIT_nCS1_BITPOS);

  /* Assign the PGWST/WELEN value */
  tmp &= ~EMIFS_PGWST_WELEN_nCS1_MSK;
  tmp |= (PGWST_WELEN << EMIFS_PGWST_WELEN_nCS1_BITPOS);

  /* Assign the BW value */
  tmp &= ~EMIFS_BUS_WIDTH_nCS1_MSK;
  tmp |= (BW << EMIFS_BUS_WIDTH_nCS1_BITPOS);

  /* Assign the Flash Intel value */
  tmp &= ~EMIFS_INTEL_FLASH_nCS1_MSK;
  tmp |= (FL << EMIFS_INTEL_FLASH_nCS1_BITPOS);

  /* Assign the Multiplexed Address/Data value */
  tmp &= ~EMIFS_MAD_nCS1_MSK;
  tmp |= (MAD << EMIFS_MAD_nCS1_BITPOS);

  /* Assign the BTWST value */
  tmp &= ~EMIFS_BT_WAIT_nCS1_MSK;
  tmp |= (BTWST << EMIFS_BT_WAIT_nCS1_BITPOS);

  /* Assign the FCLKDIV value */
  tmp &= ~EMIFS_FCLKDIV_nCS1_MSK;
  tmp |= (FCLKDIV << EMIFS_FCLKDIV_nCS1_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS1_CONFIG_REG = tmp;
}

//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigNCs2Reg
//
// DESCRIPTION  : For programming the CS2 Configuration register
//		  field bits 
//                                       
// PARAMETERS   : BTWST, MAD, FL, BW, RDMODE, PGWST_WELEN, WRWST, RDWST and 
//		  FCLKDIV.
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigNCs2Reg (	UWORD8 BTWST,
				UWORD8 MAD,
				UWORD8 FL,
				UWORD8 BW,
				UWORD8 RDMODE,
				UWORD8 PGWST_WELEN,
				UWORD8 WRWST,
				UWORD8 RDWST,
				UWORD8 FCLKDIV)
{
  UWORD32 tmp;

  /* Read the nCS2 config register */
  tmp = *(UWORD32*)EMIFS_nCS2_CONFIG_REG;

  /* Assign the RDWST value */
  tmp &= ~EMIFS_RD_WAIT_nCS2_MSK;
  tmp |= (RDWST << EMIFS_RD_WAIT_nCS2_BITPOS);

  /* Assign the RDMODE value */
  tmp &= ~EMIFS_RD_MODE_SEL_nCS2_MSK;
  tmp |= (RDMODE << EMIFS_RD_MODE_SEL_nCS2_BITPOS);

  /* Assign the WRWST value */
  tmp &= ~EMIFS_WR_WAIT_nCS2_MSK;
  tmp |= (WRWST << EMIFS_WR_WAIT_nCS2_BITPOS);

  /* Assign the PGWST/WELEN value */
  tmp &= ~EMIFS_PGWST_WELEN_nCS2_MSK;
  tmp |= (PGWST_WELEN << EMIFS_PGWST_WELEN_nCS2_BITPOS);

  /* Assign the BW value */
  tmp &= ~EMIFS_BUS_WIDTH_nCS2_MSK;
  tmp |= (BW << EMIFS_BUS_WIDTH_nCS2_BITPOS);

  /* Assign the Flash Intel value */
  tmp &= ~EMIFS_INTEL_FLASH_nCS2_MSK;
  tmp |= (FL << EMIFS_INTEL_FLASH_nCS2_BITPOS);

  /* Assign the Multiplexed Address/Data value */
  tmp &= ~EMIFS_MAD_nCS2_MSK;
  tmp |= (MAD << EMIFS_MAD_nCS2_BITPOS);

  /* Assign the BTWST value */
  tmp &= ~EMIFS_BT_WAIT_nCS2_MSK;
  tmp |= (BTWST << EMIFS_BT_WAIT_nCS2_BITPOS);

  /* Assign the FCLKDIV value */
  tmp &= ~EMIFS_FCLKDIV_nCS2_MSK;
  tmp |= (FCLKDIV << EMIFS_FCLKDIV_nCS2_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS2_CONFIG_REG = tmp;
}

//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigNCs3Reg
//
// DESCRIPTION  : For programming the CS3 Configuration register
//		  field bits 
//                                       
// PARAMETERS   : BTWST, MAD, FL, BW, RDMODE, PGWST_WELEN, WRWST, RDWST and 
//		  FCLKDIV.
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigNCs3Reg (	UWORD8 BTWST,
				UWORD8 MAD,
				UWORD8 FL,
				UWORD8 BW,
				UWORD8 RDMODE,
				UWORD8 PGWST_WELEN,
				UWORD8 WRWST,
				UWORD8 RDWST,
				UWORD8 FCLKDIV)
{
  UWORD32 tmp;

  /* Read the nCS3 config register */
  tmp = *(UWORD32*)EMIFS_nCS3_CONFIG_REG;

  /* Assign the RDWST value */
  tmp &= ~EMIFS_RD_WAIT_nCS3_MSK;
  tmp |= (RDWST << EMIFS_RD_WAIT_nCS3_BITPOS);

  /* Assign the RDMODE value */
  tmp &= ~EMIFS_RD_MODE_SEL_nCS3_MSK;
  tmp |= (RDMODE << EMIFS_RD_MODE_SEL_nCS3_BITPOS);

  /* Assign the WRWST value */
  tmp &= ~EMIFS_WR_WAIT_nCS3_MSK;
  tmp |= (WRWST << EMIFS_WR_WAIT_nCS3_BITPOS);

  /* Assign the PGWST/WELEN value */
  tmp &= ~EMIFS_PGWST_WELEN_nCS3_MSK;
  tmp |= (PGWST_WELEN << EMIFS_PGWST_WELEN_nCS3_BITPOS);

  /* Assign the BW value */
  tmp &= ~EMIFS_BUS_WIDTH_nCS3_MSK;
  tmp |= (BW << EMIFS_BUS_WIDTH_nCS3_BITPOS);

  /* Assign the Flash Intel value */
  tmp &= ~EMIFS_INTEL_FLASH_nCS3_MSK;
  tmp |= (FL << EMIFS_INTEL_FLASH_nCS3_BITPOS);

  /* Assign the Multiplexed Address/Data value */
  tmp &= ~EMIFS_MAD_nCS3_MSK;
  tmp |= (MAD << EMIFS_MAD_nCS3_BITPOS);

  /* Assign the BTWST value */
  tmp &= ~EMIFS_BT_WAIT_nCS3_MSK;
  tmp |= (BTWST << EMIFS_BT_WAIT_nCS3_BITPOS);

  /* Assign the FCLKDIV value */
  tmp &= ~EMIFS_FCLKDIV_nCS3_MSK;
  tmp |= (FCLKDIV << EMIFS_FCLKDIV_nCS3_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS3_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigReg
//
// DESCRIPTION  : For programming the  EMIFS Configuration register
//		  field bits 
//                                       
// PARAMETERS   : PDE, PWD_EN, WP.
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------
void EMIF_ConfigReg (		UWORD8 PDE,
				UWORD8 PWD_EN,
				UWORD8 WP)
{
  UWORD32 tmp;