📄 i2c.c
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else
{
I2C_Config_read_mode(0);
I2CADDRESS(address);
}
I2CSTART;
if (polorint == 1)
if (!I2C_WaitCompletedTransfer()) return RES_BAD;
else if (polorint == 0)
for (i=0;i<MAX_SOFT_WD_VALUE;i++)
{
if (I2C_IrqCount == 1) break;
if (i==MAX_SOFT_WD_VALUE) return RES_BAD;
}
errdev = I2C_IsErrorDevice();
if (errdev == I2C_IS)
return RES_BAD;
if ((I2C_DATA_READ_REG) != data)
return RES_BAD;
return RES_OK;
}
/*******************************************************************************
NAME : I2C_EepromClear
SYNOPSIS : UWORD32 I2C_EepromClear (UWORD8 device
DESCRIPTION : Clear the E2PROM
PARAMETERS : - device is the address of the select device
RETURN VALUE : the return value is RES_OK if no problem occured.
LIMITATIONS : device must be valid.
********************************************************************************/
UWORD32 I2C_EepromClear (UWORD8 device,UWORD32 value)
{
UWORD32 errdev, fifo,i;
I2C_IrqCount = 0;
I2CNO_SOFT_RESET;
I2C_CLOCK_ENABLE;
I2CWRITE;
I2CDEVICE(device);
I2CADDRESS(0);
for (i=0;i<128;i++)
if (I2CFIFO_FULL == 0)
I2CDATA_TO_WRITE(value);
I2CSTART;
if (!I2C_WaitCompletedTransfer()) return RES_BAD;
errdev = I2C_IsErrorDevice();
if (errdev == I2C_IS)
return RES_BAD;
return RES_OK;
}
/***************************************************************
test 1 : check if the value of the command, configuration and
status registers are correct
***************************************************************/
UWORD32 I2C_TestI2cReset(UWORD32 *i2cres)
{
UWORD32 i2cerror=0;
/* Device Register */
if (I2C_DEVICE_REG != 0x80)
{
*(i2cres++) = I2CERROR_DEVICE;
i2cerror = 1;
}
/* Address Register */
if (I2C_ADDRESS_REG != 0x00)
{
*(i2cres++) = I2CERROR_ADDRESS;
i2cerror = 1;
}
/* Data write Register */
if (I2C_DATA_WRITE_REG != 0x00)
{
*(i2cres++) = I2CERROR_DATA_WRITE;
i2cerror = 1;
}
/* Data Read Register */
if (I2C_DATA_READ_REG != 0x00)
{
*(i2cres++) = I2CERROR_DATA_READ;
i2cerror = 1;
}
/* Command Register */
if (I2C_CMD_REG != 0xd1)
{
*(i2cres++) = I2CERROR_CMD_REG;
i2cerror = 1;
}
/* Configuration FIFO Register */
if (I2C_CONF_FIFO_REG != 0xff)
{
*(i2cres++) = I2CERROR_CONF_FIFO_REG;
i2cerror = 1;
}
/* Configuration Clock Register */
if (I2C_CONF_CLK_REG != 0xc0)
{
*(i2cres++) = I2CERROR_CONF_CLK_REG;
i2cerror = 1;
}
/* Configuration Clock Functional Reference Register */
if (I2C_CONF_CLK_REF_REG != 0x8a)
{
*(i2cres++) = I2CERROR_CLK_FUNC_REF_REG ;
i2cerror = 1;
}
/* Status FIFO Register */
if (I2C_STATUS_FIFO_REG != 0xc2)
{
*(i2cres++) = I2CERROR_STATUS_FIFO_REG;
i2cerror = 1;
}
/* Status Activity Register */
I2C_CLOCK_ENABLE;
if (I2C_STATUS_ACTIVITY_REG != 0xf0)
{
*(i2cres++) = I2CERROR_STATUS_ACTIVITY_REG;
i2cerror = 1;
}
I2C_CLOCK_DISABLE;
if ( i2cerror == 1 )
{
return RES_BAD;
}
return RES_OK;
}
/******************************************************************
test 2 : check the value written to the command and configuration
registers can be read back and are kept after a SW reset.
Check also the others values are not changed
******************************************************************/
UWORD32 I2C_TestI2cWrRegisters(UWORD32 speed)
{
UWORD32 i2cerror=0;
UWORD32 i;
UWORD8 a;
I2CSOFT_RESET;
for(i=1;i<=10;i++);
I2CNO_SOFT_RESET;
for(i=1;i<=10;i++);
/* Write to the Command and Configuration Registers
Read access, simple read, standard mode, SPIKE=3,
FIFO SIZE is 7, interrupts disable */
I2C_Config_read_mode(1);
I2C_Config(speed,3,7,0);
/* Device Register */
(I2C_DEVICE_REG)&=(0x7f);
(I2C_DEVICE_REG)=0x55;
/* Address Register */
(I2C_ADDRESS_REG) = (0x20);
/* Data Write register */
(I2C_DATA_WRITE_REG)= (0x50);
/* Data Read register */
(I2C_DATA_READ_REG)= (0x50);
/***** Check if the values written are RES_OK *****/
/* Device Register */
if (((I2C_DEVICE_REG)&(0x7f)) != (0x55))
{
RES_Set(I2CERROR_DEVICE);
i2cerror = 1;
}
/* Address Register */
if ((I2C_ADDRESS_REG) != (0x20))
{
RES_Set(I2CERROR_ADDRESS);
i2cerror = 1;
}
/* Data Write register */
if ((I2C_DATA_WRITE_REG) != (0x50))
{
RES_Set(I2CERROR_DATA_WRITE);
i2cerror = 1;
}
/* Command Register */
if (((I2C_CMD_REG)&(0x38)) != (0x08))
{
RES_Set(I2CERROR_CMD_REG);
i2cerror = 1;
}
/* Configuration FIFO Register */
if ( (I2C_CONF_FIFO_REG) !=(0xf6))
{
RES_Set(I2CERROR_CONF_FIFO_REG);
i2cerror = 1;
}
/* Configuration Clock Register */
if (speed == 100)
{
if (I2C_CONF_CLK_REG != 0xd2)
{
RES_Set(I2CERROR_CONF_CLK_REG);
i2cerror = 1;
}
}
if (speed == 400)
{
if ((I2C_CONF_CLK_REG) != 0xd0)
{
RES_Set(I2CERROR_CONF_CLK_REG);
i2cerror = 1;
}
}
/* Configuration Clock Functional Reference Register */
if ((I2C_CONF_CLK_REF_REG) !=( 0x8a))
{
RES_Set(I2CERROR_CLK_FUNC_REF_REG);
i2cerror = 1;
}
/* Execute a soft reset and check the values written */
// I2CSOFT_RESET;
I2CSOFT_RESET;
for(i=1;i<=10;i++) ;
I2CNO_SOFT_RESET;
for(i=1;i<=10;i++) ;
/* Device Register : not affected */
if (((I2C_DEVICE_REG)&(0x7f)) != ((0x55)))
{
RES_Set(I2CERROR_DEVICE);
i2cerror=1;
}
/* Address Register : not affected */
if ( (I2C_ADDRESS_REG) != (0x20))
{
RES_Set(I2CERROR_ADDRESS);
i2cerror=1;
}
/* Data write registers : affected */
if ((I2C_DATA_WRITE_REG) != (0x00))
{
RES_Set(I2CERROR_DATA_WRITE);
i2cerror=1;
}
/* Command register : not affected */
if (((I2C_CMD_REG)&(0x38)) != (0x08))
{
RES_Set(I2CERROR_CMD_REG);
i2cerror = 1;
}
/* Configuration FIFO Register : : not affected */
if ((I2C_CONF_FIFO_REG) != (0xf6))
{
RES_Set(I2CERROR_CONF_FIFO_REG);
i2cerror = 1;
}
/* Configuration Clock Register : not affected */
if (speed == 100)
{
if (I2C_CONF_CLK_REG != 0xd2)
{
RES_Set(I2CERROR_CONF_CLK_REG);
i2cerror = 1;
}
}
if (speed == 400)
{
if (I2C_CONF_CLK_REG != 0xd0)
{
RES_Set(I2CERROR_CONF_CLK_REG);
i2cerror = 1;
}
}
/* Configuration Clock Functional Reference Register : not affected */
if ((I2C_CONF_CLK_REF_REG ) != (0x8a))
{
RES_Set(I2CERROR_CLK_FUNC_REF_REG);
i2cerror = 1;
}
/* Status FIFO register : affected */
if (( (I2C_STATUS_FIFO_REG) & (0x3f) != 0x02))
{
RES_Set(I2CERROR_STATUS_FIFO_REG);
i2cerror=1;
}
I2C_CLOCK_ENABLE;
/* Status Activity register : affected */
if ( ((I2C_STATUS_ACTIVITY_REG) & (0x0f) != 0x00))
{
RES_Set(I2CERROR_STATUS_ACTIVITY_REG);
i2cerror=1;
}
I2C_CLOCK_DISABLE;
I2CNO_SOFT_RESET;
if ( i2cerror == 1 )
return RES_BAD;
RES_Set(TEST_OK);
return RES_OK;
}
/********************************
Test 3 : 1 then 7 values in FIFO
soft reset
1 then 15 values in FIFO
Interrupts used
********************************/
UWORD32 I2C_TestI2cTransferInt(UWORD32 speed)
{
UWORD32 i2cerror=0;
UWORD32 i;
I2CSOFT_RESET;
for(i=1;i<=10;i++) ;
I2CNO_SOFT_RESET;
for(i=1;i<=10;i++) ;
// I2C_CLOCK_ENABLE;
/*-------------------------------------------------------------------------------*/
/* Write 1 value */
if (I2C_Config(speed,3,1,1) != RES_OK)
{
RES_Set(I2CERROR_DURING_CONFIG);
i2cerror=1;
}
if (I2C_Write(85,100,1,1,0,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_WRITE);
i2cerror=1;
}
/* Check the value written */
if (I2C_Read(85,100,1,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_READ);
i2cerror=1;
}
/*-------------------------------------------------------------------------------*/
/* 7 values */
if (I2C_Config(speed,3,7,1) != RES_OK)
{
RES_Set(I2CERROR_DURING_CONFIG);
i2cerror=1;
}
if (I2C_Write(85,100,2,7,0,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_WRITE);
i2cerror=1;
}
/* Check the values written */
if (I2C_Read(85,100,2,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_READ);
i2cerror=1;
}
for (i=1;i<=6;i++)
{
if (I2C_Read(85,0,2+i,1,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_READ);
i2cerror=1;
}
}
/*-------------------------------------------------------------------------------*/
/* Soft reset */
I2CSOFT_RESET;
for (i=1;i<=10;i++);
I2CNO_SOFT_RESET;
/*-------------------------------------------------------------------------------*/
/* Write 1 value */
if (I2C_Config(speed,3,1,1) != RES_OK)
{
RES_Set(I2CERROR_DURING_CONFIG);
i2cerror=1;
}
if (I2C_Write(85,100,3,1,0,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_WRITE);
i2cerror=1;
}
/* Check the value written */
if (I2C_Read(85,100,3,0,0) == RES_BAD)
{
RES_Set(I2CERROR_DURING_READ);
i2cerror=1;
}
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