inth2ab.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

     
  switch (ActivItIndexLev1)
  {
    // If the interrupt comes from the Level 2A Interrupt Handler IRQ line.
    case LEV2A_IRQ_INT :
    {
      // Get Level 2A interrupt's index
      ActivItIndexLev2=(*(UWORD8 *)(L2A_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      // Clear the ITR register of Level 2A Interrupt Handler
      ClearBitIndex(REG32(L2A_INTH_ITR_ADDR),ActivItIndexLev2);
      // Valid next IRQ on Level 2A Interrupt Handler
      SetBitIndex(REG32(L2A_INTH_CONTROL_ADDR),INTH_IRQ);
      break;
    }

    // If the interrupt comes from the Level 2A Interrupt Handler FIQ line.
    case LEV2A_FIQ_INT :
    {
      // Get Level 2A interrupt's index
      ActivItIndexLev2=(*(UWORD8 *)(L2A_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      // Clear the ITR register of Level 2A Interrupt Handler
      ClearBitIndex(REG32(L2A_INTH_ITR_ADDR),ActivItIndexLev2);
      // Valid next IRQ on Level 2A Interrupt Handler
      SetBitIndex(REG32(L2A_INTH_CONTROL_ADDR),INTH_FIQ);
      break;
    }

    // If the interrupt comes from the Level 2B Interrupt Handler IRQ line.
    case LEV2B_IRQ_INT :
    {
      // Get Level 2B interrupt's index
      ActivItIndexLev2=(*(UWORD8 *)(L2B_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      // Clear the ITR register of Level 2B Interrupt Handler
      ClearBitIndex(REG32(L2B_INTH_ITR_ADDR),ActivItIndexLev2);
      // Valid next IRQ on Level 2B Interrupt Handler
      SetBitIndex(REG32(L2B_INTH_CONTROL_ADDR),INTH_IRQ);
      break;
    }

    // If the interrupt comes from the Level 2B Interrupt Handler FIQ line.
    case LEV2B_FIQ_INT :
    {
      // Get Level 2B interrupt's index
      ActivItIndexLev2=(*(UWORD8 *)(L2B_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      // Clear the ITR register of Level 2B Interrupt Handler
      ClearBitIndex(REG32(L2B_INTH_ITR_ADDR),ActivItIndexLev2);
      // Valid next IRQ on Level 2B Interrupt Handler
      SetBitIndex(REG32(L2B_INTH_CONTROL_ADDR),INTH_FIQ);
      break;
    }

    default : break;
  }

  // Clear the ITR register of Level 1 Interrupt Handler
  ClearBitIndex(REG32(L1_INTH_ITR_ADDR),ActivItIndexLev1);
  // Valid next IRQ on Level 1 Interrupt Handler
  SetBitIndex(REG32(L1_INTH_CONTROL_ADDR),Fiq_or_Irq);
}


//########################################################################################
// NAME        : INTH2AB_ClearInt                                                 
//
// DESCRIPTION : Clear one interrupt
//               
// PARAMETERS  : ItIndex
//
// RETURN VALUE: None       
//
// LIMITATIONS : None                            
//########################################################################################
void INTH2AB_ClearInt(UWORD8 ItIndex)
{
  // Test if the interrupt comes from the Level 1 Interrupt Handler
  if ( ItIndex < 32 ) {
    // Clear the ITR register of Level 1 Interrupt Handler
    ClearBitIndex(REG32(L1_INTH_ITR_ADDR),ItIndex);
  }
  // Test if the interrupt comes from the Level 2A Interrupt Handler
  else if ( (32 <= ItIndex) && (ItIndex < 64) ) {
    // Clear the ITR register of Level 2A Interrupt Handler
    ClearBitIndex(REG32(L2A_INTH_ITR_ADDR),(ItIndex-32));
  }
  else {
    // Clear the ITR register of Level 2B Interrupt Handler
    ClearBitIndex(REG32(L2B_INTH_ITR_ADDR),(ItIndex-64));
  }
}


//########################################################################################
// NAME        : INTH2AB_EnableOneItLevel1
//
// DESCRIPTION : Enable one interrupt.
//
// PARAMETERS  : ItIndex
//
// RETURN VALUE: None         
//
// LIMITATIONS : None
//########################################################################################
void INTH2AB_EnableOneItLevel1(UWORD8 ItIndex)
{
  if(ItIndex<32) {
    // Clear the ITR register of Level 1 Interrupt Handler
    ClearBitIndex(REG32(L1_INTH_ITR_ADDR),ItIndex);
    // Unmask the interrupt line
    ClearBitIndex(REG32(L1_INTH_MIR_ADDR),ItIndex);
  }
}


//########################################################################################
// NAME        : INTH2AB_EnableOneItLevel2
//
// DESCRIPTION : Enable one interrupt. If the interrupt is on level 2 interrupt handler,
//               then the interrupt line of level 1 interrupt handler corresponding to
//               the Fiq_or_Irq parameter is also enabled.
//
// PARAMETERS  : ItIndex
//
//               Fiq_or_Irq: INTH_IRQ or INTH_FIQ (generated by level 2 interrupt handler)
//
// RETURN VALUE: None         
//
// LIMITATIONS : None
//########################################################################################
void INTH2AB_EnableOneItLevel2(UWORD8 ItIndex, BOOL Fiq_or_Irq)
{
  // Test if the interrupt comes from the Level 1 Interrupt Handler
  if(ItIndex<32) {
    // Clear the ITR register of Level 1 Interrupt Handler
    ClearBitIndex(REG32(L1_INTH_ITR_ADDR),ItIndex);
    // Unmask the interrupt line
    ClearBitIndex(REG32(L1_INTH_MIR_ADDR),ItIndex);
  }
  // Test if the interrupt comes from the Level 2A Interrupt Handler
  else if ( (32 <= ItIndex) && (ItIndex < 64) ) {
    // Clear the ITR register of Level 2A Interrupt Handler
    ClearBitIndex(REG32(L2A_INTH_ITR_ADDR),(ItIndex-32));
    // Unmask the interrupt line
    ClearBitIndex(REG32(L2A_INTH_MIR_ADDR),(ItIndex-32));
    if (Fiq_or_Irq==INTH_FIQ) {
      // Clear the ITR register of Level 1 Interrupt Handler
      ClearBitIndex(REG32(L1_INTH_ITR_ADDR),LEV2A_FIQ_INT);
      // Unmask the Level 1 LEV2A_FIQ_INT interrupt line
      ClearBitIndex(REG32(L1_INTH_MIR_ADDR),LEV2A_FIQ_INT);
    }
    else {
      // Clear the ITR register of Level 1 Interrupt Handler
      ClearBitIndex(REG32(L1_INTH_ITR_ADDR),LEV2A_IRQ_INT);
      // Unmask the Level 1 LEV2A_IRQ_INT interrupt line
      ClearBitIndex(REG32(L1_INTH_MIR_ADDR),LEV2A_IRQ_INT);
    }
  }
  else {
    // Clear the ITR register of Level 2B Interrupt Handler
    ClearBitIndex(REG32(L2B_INTH_ITR_ADDR),(ItIndex-64));
    // Unmask the interrupt line
    ClearBitIndex(REG32(L2B_INTH_MIR_ADDR),(ItIndex-64));
    if (Fiq_or_Irq==INTH_FIQ) {
      // Clear the ITR register of Level 1 Interrupt Handler
      ClearBitIndex(REG32(L1_INTH_ITR_ADDR),LEV2B_FIQ_INT);
      // Unmask the Level 1 LEV2B_FIQ_INT interrupt line
      ClearBitIndex(REG32(L1_INTH_MIR_ADDR),LEV2B_FIQ_INT);
    }
    else {
      // Clear the ITR register of Level 1 Interrupt Handler
      ClearBitIndex(REG32(L1_INTH_ITR_ADDR),LEV2B_IRQ_INT);
      // Unmask the Level 1 LEV2B_IRQ_INT interrupt line
      ClearBitIndex(REG32(L1_INTH_MIR_ADDR),LEV2B_IRQ_INT);
    }
  }
}


//########################################################################################
// NAME        : INTH2AB_DisableOneIt                                                 
//
// DESCRIPTION : Mask one interrupt. If the interrupt is on level 2 interrupt handler and
//               if there is no more unmasked interrupt on level 2, then the interrupt
//               lines incomming from level 2 to level1 are also masked.
//
// PARAMETERS  : ItIndex 
//
// RETURN VALUE: None         
//
// LIMITATIONS : None                            
//########################################################################################
void INTH2AB_DisableOneIt(UWORD8 ItIndex)
{
  // Test if the interrupt comes from the Level 1 Interrupt Handler
  if (ItIndex<32) {
    // Mask the interrupt on Level 1 Interrupt Handler
    *(UWORD32*)L1_INTH_MIR_ADDR |= (1 << ItIndex);
  }
  // Test if the interrupt comes from the Level 2A Interrupt Handler
  else if ( (32 <= ItIndex) && (ItIndex < 64) ) {
    // Mask the interrupt on Level 2A Interrupt Handler
    *(UWORD32*)L2A_INTH_MIR_ADDR |= (1 << (ItIndex-32));
    if (REG32(L2A_INTH_MIR_ADDR)==L1_INTH_MIR_IRQ_X_MSK_RES_VAL) {
      // Mask the LEV2A_FIQ_INT interrupt on Level 1 Interrupt Handler
      *(UWORD32*)L1_INTH_MIR_ADDR |= (1 << LEV2A_FIQ_INT);
      // Mask the LEV2A_IRQ_INT interrupt on Level 1 Interrupt Handler
      *(UWORD32*)L1_INTH_MIR_ADDR |= (1 << LEV2A_IRQ_INT);
    }
  }
  else {
    // Mask the interrupt on Level 2B Interrupt Handler
    *(UWORD32*)L2B_INTH_MIR_ADDR |= (1 << (ItIndex-64));
    if (REG32(L2B_INTH_MIR_ADDR)==L1_INTH_MIR_IRQ_X_MSK_RES_VAL) {
      // Mask the LEV2B_FIQ_INT interrupt on Level 1 Interrupt Handler
      *(UWORD32*)L1_INTH_MIR_ADDR |= (1 << LEV2B_FIQ_INT);
      // Mask the LEV2B_IRQ_INT interrupt on Level 1 Interrupt Handler
      *(UWORD32*)L1_INTH_MIR_ADDR |= (1 << LEV2B_IRQ_INT);
    }
  }
}