inth2ab.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 2001, (C) Copyright 2001 Texas Instruments.  All rights reserved.
//===============================================================================
#include  "inth2ab.h"


//############################################################################
// NAME        : INTH2AB_InitLevel1
//
// DESCRIPTION : Configures the ILR register's of Level 1 interrupt handler
//               (in case of one peripheral interrupt incomming in level 1
//               interrupt handler)
//
// PARAMETERS  : ItIndex
//
//               Fiq_or_Irq: INTH_FIQ or INTH_IRQ
//
//               Priority
//
//               SensitiveEdge: FALLING_EDGE_SENSITIVE or LOW_LEVEL_SENSITIVE
//
// RETURN VALUE: None
//
// LIMITATIONS : None                                                        
//############################################################################
void INTH2AB_InitLevel1 (UWORD8   ItIndex, 
                        BOOL     Fiq_or_Irq,
                        UWORD8   Priority,
                        BOOL     SensitiveEdge)
{
volatile UWORD32* PtLevelReg;
   
  if (ItIndex<32) {
    // Level 1 Interrupt Handler
    PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + ItIndex;
    *PtLevelReg = ( (Fiq_or_Irq     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                   | (Priority      << L1_INTH_ILR_IRQ_0_PRIORITY_POS) 
                   | (SensitiveEdge << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));
  }
}


//############################################################################
// NAME        : INTH2AB_InitLevel2
//
// DESCRIPTION : Configures the ILR register's of Level 1 and Level 2 interrupt
//               handler (in case of one peripheral interrupt incomming in
//               Level 2 interrupt handler)
//
// PARAMETERS  : ItIndex
//
//               Fiq_or_Irq_Lev1: INTH_FIQ or INTH_IRQ (Level 1)
//
//               Priority_Lev1: (Level 1)
//
//               SensitiveEdge_Lev1: FALLING_EDGE_SENSITIVE or LOW_LEVEL_SENSITIVE (Level 1)
//
//               Fiq_or_Irq_Lev2: INTH_FIQ or INTH_IRQ (Level 2)
//
//               Priority_Lev2: (Level 2)
//
//               SensitiveEdge_Lev2: FALLING_EDGE_SENSITIVE or LOW_LEVEL_SENSITIVE (Level 2)
//
// RETURN VALUE: None
//
// LIMITATIONS : None                                                        
//############################################################################
void INTH2AB_InitLevel2 (UWORD8   ItIndex, 
                        BOOL     Fiq_or_Irq_Lev1,
                        UWORD8   Priority_Lev1,
                        BOOL     SensitiveEdge_Lev1,
                        BOOL     Fiq_or_Irq_Lev2,
                        UWORD8   Priority_Lev2,
                        BOOL     SensitiveEdge_Lev2)
{
volatile UWORD32* PtLevelReg;
   
  if (ItIndex<32) {
    // Level 1 Interrupt Handler
    PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + ItIndex;
    *PtLevelReg = ( (Fiq_or_Irq_Lev1     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                   | (Priority_Lev1      << L1_INTH_ILR_IRQ_0_PRIORITY_POS) 
                   | (SensitiveEdge_Lev1 << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));
  }
  else if ((32 <= ItIndex) && (ItIndex < 64)) {
    // Level 2A Interrupt Handler
    // Configure Level 2A Interrupt Handler to generate Fiq or Irq on Level 1 Interrupt Handler
    PtLevelReg = (UWORD32*)L2A_INTH_ILR_IRQ_0_ADDR + (ItIndex-32);
    *PtLevelReg = ( (Fiq_or_Irq_Lev2     << L2A_INTH_ILR_IRQ_0_FIQ_POS)
                   | (Priority_Lev2      << L2A_INTH_ILR_IRQ_0_PRIORITY_POS) 
                   | (SensitiveEdge_Lev2 << L2A_INTH_ILR_IRQ_0_SENS_EDGE_POS));
    // Configure Level 1 Interrupt Handler to generate Fiq or Irq when receive LEV2A_IRQ_INT or LEV2A_FIQ_INT
    if (Fiq_or_Irq_Lev2 == INTH_IRQ) {
      PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + LEV2A_IRQ_INT;
      *PtLevelReg = ( (Fiq_or_Irq_Lev1     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                     | (Priority_Lev1      << L1_INTH_ILR_IRQ_0_PRIORITY_POS)
                     | (SensitiveEdge_Lev1 << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));
    }
    else {
      PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + LEV2A_FIQ_INT;
      *PtLevelReg = ( (Fiq_or_Irq_Lev1     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                     | (Priority_Lev1      << L1_INTH_ILR_IRQ_0_PRIORITY_POS)
                     | (SensitiveEdge_Lev1 << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));
    }
  }
  else {
    // Level 2B Interrupt Handler
    // Configure Level 2B Interrupt Handler to generate Fiq on Level 1 Interrupt Handler
    PtLevelReg = (UWORD32*)L2B_INTH_ILR_IRQ_0_ADDR + (ItIndex-64);
    *PtLevelReg = ( (Fiq_or_Irq_Lev2     << L2B_INTH_ILR_IRQ_0_FIQ_POS)
                   | (Priority_Lev2      << L2B_INTH_ILR_IRQ_0_PRIORITY_POS) 
                   | (SensitiveEdge_Lev2 << L2B_INTH_ILR_IRQ_0_SENS_EDGE_POS));
    // Configure Level 1 Interrupt Handler to generate Fiq or Irq when receive LEV2B_IRQ_INT or LEV2B_FIQ_INT
    if (Fiq_or_Irq_Lev2 == INTH_IRQ) {
      PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + LEV2B_IRQ_INT;
      *PtLevelReg = ( (Fiq_or_Irq_Lev1     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                     | (Priority_Lev1      << L1_INTH_ILR_IRQ_0_PRIORITY_POS) 
                     | (SensitiveEdge_Lev1 << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));	
    }
    else {
      PtLevelReg = (UWORD32*)L1_INTH_ILR_IRQ_0_ADDR + LEV2B_FIQ_INT;
      *PtLevelReg = ( (Fiq_or_Irq_Lev1     << L1_INTH_ILR_IRQ_0_FIQ_POS)
                     | (Priority_Lev1      << L1_INTH_ILR_IRQ_0_PRIORITY_POS) 
                     | (SensitiveEdge_Lev1 << L1_INTH_ILR_IRQ_0_SENS_EDGE_POS));	
    }
  }
}


//########################################################################################
// NAME        : INTH2AB_GetCurrentIt                                                 
//
// DESCRIPTION : Get the current It and valid the next one
//
// PARAMETERS  : Fiq_or_Irq: INTH_IRQ or INTH_FIQ (generated by level 1 interrupt handler)
//
// RETURN VALUE: Number of the active and acknowledged Interrupt          
//
// LIMITATIONS : Must be called on Incoming IT                            
//########################################################################################
UWORD8 INTH2AB_GetCurrentIt (BOOL Fiq_or_Irq)
{
UWORD8 ActivItIndex;

  if (Fiq_or_Irq == INTH_IRQ) {
    ActivItIndex=(*(UWORD8 *)(L1_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
  }
  else
  {
    ActivItIndex=(*(UWORD8 *)(L1_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
  }

  switch (ActivItIndex)
  {
    // If the interrupt comes from the Level 2A Interrupt Handler IRQ line.
    case LEV2A_IRQ_INT :
    {
      ActivItIndex=(*(UWORD8 *)(L2A_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      ActivItIndex=ActivItIndex+32;
      break;
    }

    // If the interrupt comes from the Level 2A Interrupt Handler FIQ line.
    case LEV2A_FIQ_INT :
    {
      ActivItIndex=(*(UWORD8 *)(L2A_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      ActivItIndex=ActivItIndex+32;
      break;
    }

    // If the interrupt comes from the Level 2B Interrupt Handler IRQ line.
    case LEV2B_IRQ_INT :
    {
      ActivItIndex=(*(UWORD8 *)(L2B_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      ActivItIndex=ActivItIndex+64;
      break;
    }

    // If the interrupt comes from the Level 2B Interrupt Handler FIQ line.
    case LEV2B_FIQ_INT :
    {
      ActivItIndex=(*(UWORD8 *)(L2B_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
      ActivItIndex=ActivItIndex+64;
      break;
    }

    default : break;
  }

  return(ActivItIndex);
}

//########################################################################################
// NAME        : INTH2AB_ValidNextInterrupt                                                 
//
// DESCRIPTION : Clear the current interrupt and valid the next one
//
// PARAMETERS  : Fiq_or_Irq: INTH_IRQ or INTH_FIQ (generated by level 1 interrupt handler)
//
// RETURN VALUE: None       
//
// LIMITATIONS : Must be called on Incoming IT                            
//########################################################################################
void INTH2AB_ValidNextInterrupt (BOOL Fiq_or_Irq)
{
UWORD16 ActivItIndexLev1, ActivItIndexLev2;

  // Get Level 1 interrupt's index
  if (Fiq_or_Irq == INTH_IRQ) {
    ActivItIndexLev1=(*(UWORD8 *)(L1_INTH_SIR_IRQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
  }
  else
  {
    ActivItIndexLev1=(*(UWORD8 *)(L1_INTH_SIR_FIQ_CODE_ADDR))&INTH_SIR_CODE_REG_MASK;
  }