pcc_ulpd.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,LDO_PWRDOWN,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
    //PCC_ULPD_POWER_CTRL_REG,LDO_STEADY is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN_RST,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
    RW_WRITE(PCC_ULPD_POWER_CTRL_REG);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,LDO_PWRDOWN,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
    //PCC_ULPD_POWER_CTRL_REG,LDO_STEADY is Read Only
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN_RST,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
    RW_TEST_READ(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_POWER_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG,SETUP_ANALOG_CELL4,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG,SETUP_ANALOG_CELL4,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG,SETUP_ANALOG_CELL5,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG,SETUP_ANALOG_CELL5,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG,SETUP_ANALOG_CELL6,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG,SETUP_ANALOG_CELL6,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SOFT_DISABLE_REQ_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK3_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK2_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK1_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_HOST_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CAM_DPLL_MCLK_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_PERIPH_NREQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_SDW_MCLK_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_COM_MCLK_REQ,16);
    RW_WRITE(PCC_ULPD_SOFT_DISABLE_REQ_REG);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK3_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK2_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK1_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_HOST_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CAM_DPLL_MCLK_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_PERIPH_NREQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_SDW_MCLK_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_COM_MCLK_REQ,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SOFT_DISABLE_REQ_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_RESET_STATUS,16);
    RW_PREPARE_WRITE(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
    RW_PREPARE_WRITE(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
    RW_PREPARE_WRITE(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
    RW_PREPARE_WRITE(PCC_ULPD_RESET_STATUS,POWER_ON_RESET,16);
    RW_WRITE(PCC_ULPD_RESET_STATUS);
    RW_TEST_READ(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
    RW_TEST_READ(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
    RW_TEST_READ(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
    RW_TEST_READ(PCC_ULPD_RESET_STATUS,POWER_ON_RESET,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_RESET_STATUS);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,16);
    RW_PREPARE_WRITE(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_RATIO_SEL,16);
    RW_PREPARE_WRITE(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_ULPD_PLL_CLK_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_SYSCLK_PLLCLK_SEL,16);
    RW_WRITE(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL);
    RW_TEST_READ(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_RATIO_SEL,16);
    RW_TEST_READ(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_ULPD_PLL_CLK_REQ,16);
    RW_TEST_READ(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_SYSCLK_PLLCLK_SEL,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,16);
    RW_PREPARE_WRITE(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_RATIO_SEL,16);
    RW_PREPARE_WRITE(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_ULPD_PLL_CLK_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_SYSCLK_PLLCLK_SEL,16);
    RW_WRITE(PCC_ULPD_COM_CLK_DIV_CTRL_SEL);
    RW_TEST_READ(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_RATIO_SEL,16);
    RW_TEST_READ(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_ULPD_PLL_CLK_REQ,16);
    RW_TEST_READ(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_SYSCLK_PLLCLK_SEL,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_COM_CLK_DIV_CTRL_SEL);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_CAM_CLK_CTRL,16);
    RW_PREPARE_WRITE(PCC_ULPD_CAM_CLK_CTRL,SYSTEM_CLK_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_CAM_CLK_CTRL,CAM_CLK_DIV,16);
    RW_PREPARE_WRITE(PCC_ULPD_CAM_CLK_CTRL,CAM_CLOCK_EN,16);
    RW_WRITE(PCC_ULPD_CAM_CLK_CTRL);
    RW_TEST_READ(PCC_ULPD_CAM_CLK_CTRL,SYSTEM_CLK_EN,16);
    RW_TEST_READ(PCC_ULPD_CAM_CLK_CTRL,CAM_CLK_DIV,16);
    RW_TEST_READ(PCC_ULPD_CAM_CLK_CTRL,CAM_CLOCK_EN,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_CAM_CLK_CTRL);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SOFT_REQ_REG2,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG2,SOFT_CLOCK3_DPLL_REQ,16);
    RW_WRITE(PCC_ULPD_SOFT_REQ_REG2);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG2,SOFT_CLOCK3_DPLL_REQ,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SOFT_REQ_REG2);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_PCC_CTRL_REG,16);
    //PCC_ULPD_PCC_CTRL_REG,RESERVED is Read Only
    //PCC_ULPD_PCC_CTRL_REG,SWITCH_STS is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_PCC_CTRL_REG,SLC_OUT_DIV,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_CTRL_REG,APLL_ALWAYS_ON,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_CTRL_REG,CLK_SWITCH_CMD,16);
    RW_WRITE(PCC_ULPD_PCC_CTRL_REG);
    //PCC_ULPD_PCC_CTRL_REG,RESERVED is Read Only
    //PCC_ULPD_PCC_CTRL_REG,SWITCH_STS is Read Only
    RW_TEST_READ(PCC_ULPD_PCC_CTRL_REG,SLC_OUT_DIV,16);
    RW_TEST_READ(PCC_ULPD_PCC_CTRL_REG,APLL_ALWAYS_ON,16);
    RW_TEST_READ(PCC_ULPD_PCC_CTRL_REG,CLK_SWITCH_CMD,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_PCC_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_PCC_POWER_CTRL_REG,16);
    //PCC_ULPD_PCC_POWER_CTRL_REG,RESERVED is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,OSC_32K_BYPASS,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,DIS_RF_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,ENABLE_SOFT_DRIVE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_PWRDN,16);
    //PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_SLEEP is Read Only
    //PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_STEADY is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_PWRDN,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_SLEEP,16);
    //PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_STEADY is Read Only
    RW_WRITE(PCC_ULPD_PCC_POWER_CTRL_REG);
    //PCC_ULPD_PCC_POWER_CTRL_REG,RESERVED is Read Only
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,OSC_32K_BYPASS,16);
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,DIS_RF_EN,16);
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,ENABLE_SOFT_DRIVE,16);
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_PWRDN,16);
    //PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_SLEEP is Read Only
    //PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_STEADY is Read Only
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_PWRDN,16);
    RW_TEST_READ(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_SLEEP,16);
    //PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_STEADY is Read Only
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_PCC_POWER_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,16);
    //PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,SYREN_PERIPH_CLK,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED2,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP2_CLK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP1_CLK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,CAM_IF_CLK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,EAC_CLK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART3_CLK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART1_CLOCK_SOURCE,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MMC_SDIO_CLK,16);
    RW_PREPARE_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,USB_OTG_CLK,16);
    RW_WRITE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL);
    //PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED is Read Only
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,SYREN_PERIPH_CLK,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED2,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP2_CLK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP1_CLK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,CAM_IF_CLK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,EAC_CLK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART3_CLK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART1_CLOCK_SOURCE,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MMC_SDIO_CLK,16);
    RW_TEST_READ(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,USB_OTG_CLK,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_PCC_APLL_LOCK_REGISTER,16);
    //PCC_ULPD_PCC_APLL_LOCK_REGISTER,APLL_LOCK is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_PCC_APLL_LOCK_REGISTER,LOCK_TIME_REG,16);
    RW_WRITE(PCC_ULPD_PCC_APLL_LOCK_REGISTER);
    //PCC_ULPD_PCC_APLL_LOCK_REGISTER,APLL_LOCK is Read Only
    RW_TEST_READ(PCC_ULPD_PCC_APLL_LOCK_REGISTER,LOCK_TIME_REG,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_PCC_APLL_LOCK_REGISTER);
    END_RW_TEST();

  END_ACCESS_MODULE();

}