pcc_ulpd.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESET_STATUS,16);
    TEST_FIELD_RESET(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
    TEST_FIELD_RESET(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
    TEST_FIELD_RESET(PCC_ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
    TEST_FIELD_RESET(PCC_ULPD_RESET_STATUS,POWER_ON_RESET,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_REVISION_NUMBER,16);
    //PCC_ULPD_REVISION_NUMBER,REVISION_NUMBER of PCC_ULPD_REVISION_NUMBER has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,16);
    TEST_FIELD_RESET(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_RATIO_SEL,16);
    TEST_FIELD_RESET(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_ULPD_PLL_CLK_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SDW_CLK_DIV_CTRL_SEL,SDW_SYSCLK_PLLCLK_SEL,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,16);
    TEST_FIELD_RESET(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_RATIO_SEL,16);
    TEST_FIELD_RESET(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_ULPD_PLL_CLK_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_COM_CLK_DIV_CTRL_SEL,COM_SYSCLK_PLLCLK_SEL,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_CAM_CLK_CTRL,16);
    TEST_FIELD_RESET(PCC_ULPD_CAM_CLK_CTRL,SYSTEM_CLK_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_CAM_CLK_CTRL,CAM_CLK_DIV,16);
    TEST_FIELD_RESET(PCC_ULPD_CAM_CLK_CTRL,CAM_CLOCK_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SOFT_REQ_REG2,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG2,SOFT_CLOCK3_DPLL_REQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PCC_CTRL_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_CTRL_REG,RESERVED,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_CTRL_REG,SYERN_CLK_SWITCH_STS,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_CTRL_REG,SLC_OUT_DIV,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_CTRL_REG,APLL_ALWAYS_ON,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_CTRL_REG,CLK_SWITCH_CMD,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PCC_POWER_CTRL_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,RESERVED,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,OSC_32K_BYPASS,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,DIS_RF_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,ENABLE_SOFT_DRIVE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_PWRDN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_SLEEP,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,MPU_LDO_STEADY,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_PWRDN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_SLEEP,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_POWER_CTRL_REG,DBB_LDO_STEADY,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,SYREN_PERIPH_CLK,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,RESERVED2,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP2_CLK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MCBSP1_CLK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,CAM_IF_CLK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,EAC_CLK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART3_CLK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,UART1_CLOCK_SOURCE,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,MMC_SDIO_CLK,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL,USB_OTG_CLK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PCC_APLL_LOCK_REGISTER,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_APLL_LOCK_REGISTER,APLL_LOCK,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_APLL_LOCK_REGISTER,LOCK_TIME_REG,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PCC_DBB_STATUS,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_DBB_STATUS,RESERVED,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_DBB_STATUS,DBB_CLK13M_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_DBB_STATUS,DBB_SLICER_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_DBB_STATUS,DBB_VTCXO_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_PCC_DBB_STATUS,DBB_RF_EN,16);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : PCC_UlpdTestRegistersAccess
//
// DESCRIPTION : Test the access to PCC_ULPD registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void PCC_UlpdTestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(PCC_ULPD_GAUGING_CTRL_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    RW_PREPARE_WRITE(PCC_ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    RW_WRITE(PCC_ULPD_GAUGING_CTRL_REG);
    RW_TEST_READ(PCC_ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    RW_TEST_READ(PCC_ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_GAUGING_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG,SETUP_ANALOG_CELL3,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG,SETUP_ANALOG_CELL3,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG,SETUP_ANALOG_CELL2,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG,SETUP_ANALOG_CELL2,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG,SETUP_ANALOG_CELL1,16);
    RW_WRITE(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG);
    RW_TEST_READ(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG,SETUP_ANALOG_CELL1,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_CLOCK_CTRL_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,DIS_USB_PVCI_CLK,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,USB_MCLK_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,TI_RESERVED_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,SDW_MCLK_INV,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,COM_MCLK_INV,16);
    RW_PREPARE_WRITE(PCC_ULPD_CLOCK_CTRL_REG,MODEM_32K_EN,16);
    RW_WRITE(PCC_ULPD_CLOCK_CTRL_REG);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,DIS_USB_PVCI_CLK,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,USB_MCLK_EN,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,TI_RESERVED_EN,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,SDW_MCLK_INV,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,COM_MCLK_INV,16);
    RW_TEST_READ(PCC_ULPD_CLOCK_CTRL_REG,MODEM_32K_EN,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_CLOCK_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_SOFT_REQ_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_EAC12M_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_MMC_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_UART3_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_UART1_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_OTG_DPLL_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_CAM_DPLL_MCKO_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP1_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,USB_REQ_EN,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP2_REQ,16);
    RW_PREPARE_WRITE(PCC_ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
    RW_WRITE(PCC_ULPD_SOFT_REQ_REG);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_EAC12M_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_MMC_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_UART3_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_UART1_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_OTG_DPLL_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_CAM_DPLL_MCKO_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP1_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,USB_REQ_EN,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP2_REQ,16);
    RW_TEST_READ(PCC_ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_SOFT_REQ_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_COUNTER_32_FIQ_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_COUNTER_32_FIQ_REG,COUNTER_32_FIQ,16);
    RW_WRITE(PCC_ULPD_COUNTER_32_FIQ_REG);
    RW_TEST_READ(PCC_ULPD_COUNTER_32_FIQ_REG,COUNTER_32_FIQ,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_COUNTER_32_FIQ_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_PLL_DIV_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_PLL_DIV_REG,PLL_DIV_FACTOR,16);
    RW_WRITE(PCC_ULPD_PLL_DIV_REG);
    RW_TEST_READ(PCC_ULPD_PLL_DIV_REG,PLL_DIV_FACTOR,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_PLL_DIV_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_ULPD_PLL_CTRL_STATUS,16);
    //PCC_ULPD_ULPD_PLL_CTRL_STATUS,LOCK_STATUS is Read Only
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PLL_CTRL_RES,16);
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PWRDNZ,16);
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,TEST,16);
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL2,16);
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL1,16);
    RW_PREPARE_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL0,16);
    RW_WRITE(PCC_ULPD_ULPD_PLL_CTRL_STATUS);
    //PCC_ULPD_ULPD_PLL_CTRL_STATUS,LOCK_STATUS is Read Only
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PLL_CTRL_RES,16);
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PWRDNZ,16);
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,TEST,16);
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL2,16);
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL1,16);
    RW_TEST_READ(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL0,16);
    RW_WRITE_PREVIOUS_VALUE(PCC_ULPD_ULPD_PLL_CTRL_STATUS);
    END_RW_TEST();

    BEGIN_RW_TEST(PCC_ULPD_POWER_CTRL_REG,16);
    RW_PREPARE_WRITE(PCC_ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);