pcc_ulpd.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : perseus2_pcc_ulpd.c
//   Date of Module Modification:7/1/02
//   Date of Generation :7/10/02
//
//===============================================================================
#include "global_types.h"
#include "pcc_ulpd.h"
#include "testaccess.h"
#include "test.h"
#include "errorcodes.h"
#include "result.h"

//---------------------------------------------------------------------
// NAME        : PCC_ULPD_TestResetValue
//
// DESCRIPTION : Test the reset values of PCC_ULPD registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void PCC_UlpdTestResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(PCC_ULPD_COUNTER_32_LSB_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_COUNTER_32_LSB_REG,COUNTER_SLEEP_CLK_LSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_COUNTER_32_MSB_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_COUNTER_32_MSB_REG,COUNTER_32_MSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG,COUNTER_HIGH_FREQ_LSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG,COUNTER_HIGH_FREQ_MSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_GAUGING_CTRL_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    TEST_FIELD_RESET(PCC_ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_IT_STATUS_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_IT_STATUS_REG,IT_WAKEUP_USB,16);
    TEST_FIELD_RESET(PCC_ULPD_IT_STATUS_REG,OVERFLOW_32,16);
    TEST_FIELD_RESET(PCC_ULPD_IT_STATUS_REG,OVERFLOW_HI_FREQ,16);
    TEST_FIELD_RESET(PCC_ULPD_IT_STATUS_REG,IT_GAUGING,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESERVED,16);
    TEST_FIELD_RESET(PCC_ULPD_RESERVED,RESERVED,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESERVED1,16);
    TEST_FIELD_RESET(PCC_ULPD_RESERVED1,RESERVED,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESERVED2,16);
    TEST_FIELD_RESET(PCC_ULPD_RESERVED2,RESERVED,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG,SETUP_ANALOG_CELL3,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG,SETUP_ANALOG_CELL2,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG,SETUP_ANALOG_CELL1,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_CLOCK_CTRL_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,DIS_USB_PVCI_CLK,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,USB_MCLK_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,TI_RESERVED_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,SDW_MCLK_INV,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,COM_MCLK_INV,16);
    TEST_FIELD_RESET(PCC_ULPD_CLOCK_CTRL_REG,MODEM_32K_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SOFT_REQ_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_RESERVED_0_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_EAC12M_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_RESERVED_1_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_MMC_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_UART3_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_RESERVED_2_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_UART1_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_OTG_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_CAM_DPLL_MCKO_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP1_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_RESERVED_NREQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,USB_REQ_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_USB_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_MCBSP2_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_RESERVED_3_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_COUNTER_32_FIQ_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_COUNTER_32_FIQ_REG,COUNTER_32_FIQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESERVED3,16);
    TEST_FIELD_RESET(PCC_ULPD_RESERVED3,RESERVED,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_STATUS_REQ_REG,16);
    //PCC_ULPD_STATUS_REQ_REG,CLOCK3_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,CLOCK2_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,CLOCK1_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,MMC_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,UART3_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,UART2_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,UART1_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,USB_HOST_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,CAM_DPLL_MCLK_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,USB_DPLL_MCLK_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,USB_MCLK_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,SDW_MCLK_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,COM_MCLK_REQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,PERIPH_NREQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,WAKEUP_NREQ of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    //PCC_ULPD_STATUS_REQ_REG,CHIP_IDLE of PCC_ULPD_STATUS_REQ_REG has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_PLL_DIV_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_PLL_DIV_REG,PLL_DIV_FACTOR,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_RESERVED4,16);
    TEST_FIELD_RESET(PCC_ULPD_RESERVED4,RESERVED,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_ULPD_PLL_CTRL_STATUS,16);
    //PCC_ULPD_ULPD_PLL_CTRL_STATUS,LOCK_STATUS of PCC_ULPD_ULPD_PLL_CTRL_STATUS has unknown reset value;
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PLL_CTRL_RES,16);
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,PWRDNZ,16);
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,TEST,16);
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL2,16);
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL1,16);
    TEST_FIELD_RESET(PCC_ULPD_ULPD_PLL_CTRL_STATUS,SEL0,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_POWER_CTRL_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,LDO_PWRDOWN,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
    //PCC_ULPD_POWER_CTRL_REG,LDO_STEADY of PCC_ULPD_POWER_CTRL_REG has unknown reset value;
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,SW_NSHUTDOWN_RST,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_STATUS_REQ_REG2,16);
    //PCC_ULPD_STATUS_REQ_REG2,MMC2_DPLL_REQ of PCC_ULPD_STATUS_REQ_REG2 has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SLEEP_STATUS,16);
    //PCC_ULPD_SLEEP_STATUS,BIG_SLEEP of PCC_ULPD_SLEEP_STATUS has unknown reset value;
    //PCC_ULPD_SLEEP_STATUS,DEEP_SLEEP of PCC_ULPD_SLEEP_STATUS has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG,SETUP_ANALOG_CELL4,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG,SETUP_ANALOG_CELL5,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG,SETUP_ANALOG_CELL6,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(PCC_ULPD_SOFT_DISABLE_REQ_REG,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK3_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK2_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CLOCK1_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_HOST_DPLL_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_CAM_DPLL_MCLK_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_PERIPH_NREQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_SDW_MCLK_REQ,16);
    TEST_FIELD_RESET(PCC_ULPD_SOFT_DISABLE_REQ_REG,DIS_COM_MCLK_REQ,16);