📄 uartcommon.c
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const UARTMOD_SleepModeToggle_t SleepMode,
const UARTMOD_XoffItToggle_t XoffIt,
const UARTMOD_RtsItToggle_t RtsIt,
const UARTMOD_CtsItToggle_t CtsIt,
UARTMOD_UartType_t UartType)
{
UWORD8 efrold, lcrold, iermodem;
//Set registers access
efrold = UMOD_SetEfr4(UartType);
lcrold = UMOD_ClearLcr7(UartType);
UARTMOD_IER_REG(UartType) = ( RhrIt |
ThrIt << 1 |
ReceiverLineStatusIt << 2 |
ModemStatusIt << 3 |
SleepMode << 4 |
XoffIt << 5 |
RtsIt << 6 |
CtsIt << 7);
iermodem = UARTMOD_IER_REG(UartType);
//Restore registers access
UMOD_RestoreEfr(efrold,UartType);
UARTMOD_LCR_REG(UartType)=lcrold;
return iermodem;
}
//-----------------------------------------
// UMOD_ModifyIer
//-----------------------------------------
UWORD8 UMOD_ModifyIer(const UARTMOD_RhrItToggle_t RhrIt,
const UARTMOD_ThrItToggle_t ThrIt,
const UARTMOD_LineStsItToggle_t ReceiverLineStatusIt,
const UARTMOD_ModemStsItToggle_t ModemStatusIt,
const UARTMOD_SleepModeToggle_t SleepMode,
const UARTMOD_XoffItToggle_t XoffIt,
const UARTMOD_RtsItToggle_t RtsIt,
const UARTMOD_CtsItToggle_t CtsIt,
UARTMOD_UartType_t UartType)
{
UWORD8 iermodem;
//Set registers access
//FH UMOD_CheckLcr7Is0(UartType);
UARTMOD_IER_REG(UartType) = ( RhrIt |
ThrIt << 1 |
ReceiverLineStatusIt << 2 |
ModemStatusIt << 3 |
SleepMode << 4 |
XoffIt << 5 |
RtsIt << 6 |
CtsIt << 7);
iermodem = UARTMOD_IER_REG(UartType);
return iermodem;
}
//------------------------------------------------
// UMOD_InitEfr
//------------------------------------------------
void UMOD_InitEfr( const UARTMOD_RxSwflowCtr_t RxSwFlowCtrol,
const UARTMOD_TxSwflowCtr_t TxSwFlowCtrol,
const UARTMOD_EnhancedEnable_t EnhEnable,
const UARTMOD_SpecialCharDetect_t SpecialCharDetect,
const UARTMOD_AutoRtsEnable_t AutoRtsEnable,
const UARTMOD_AutoCtsEnable_t AutoCtsEnable,
UARTMOD_UartType_t UartType)
{
UWORD8 lcrold;
//Store current value LCR and set it to 0xBF to access EFR
lcrold = UMOD_SetBfToLcr(UartType);
UARTMOD_EFR_REG(UartType) = ( RxSwFlowCtrol |
TxSwFlowCtrol << 2 |
EnhEnable << 4 |
SpecialCharDetect << 5 |
AutoRtsEnable << 6 |
AutoCtsEnable << 7);
//Restore LCR
UARTMOD_LCR_REG(UartType) = lcrold;
}
// UNUSED IN PERSEUS
/*
//------------------------------------------------------
// UMOD_InitUir
//------------------------------------------------------
UWORD8 UMOD_InitUir(UARTMOD_Access_t access,
UARTMOD_MaskInterrupt_t itmask,
UARTMOD_UartType_t UartType)
{
UWORD8 status;
UARTMOD_UIR_REG(UartType)= (access | itmask << 1);
status=UARTMOD_UIR_REG(UartType) ;
return status;
}
*/
//--------------------------------------------------------------
// UMOD_InitDivLatch: Setup Divisor Latches
//--------------------------------------------------------------
void UMOD_InitDivLatch(const UWORD8 dll, const UWORD8 dlh, UARTMOD_UartType_t UartType)
{
UWORD8 lcrold;
// DLL and DLH are accessible only when LCR Bit-7, is 1
//Store current value LCR and set it to 0xBF to access DLL
lcrold = UMOD_SetBfToLcr(UartType);
UARTMOD_DLL_REG(UartType) = dll;
UARTMOD_DLH_REG(UartType) = dlh;
//Restore LCR
UARTMOD_LCR_REG(UartType) = lcrold;
}
//---------------------------------------
// UMOD_ReadDll -
//---------------------------------------
UWORD8 UMOD_ReadDll(UARTMOD_UartType_t UartType)
{
UWORD8 dll, lcrold;
//Store current value LCR and set it to 0xBF to access DLL
lcrold = UMOD_SetBfToLcr(UartType);
dll = UARTMOD_DLL_REG(UartType);
//Restore LCR
UARTMOD_LCR_REG(UartType) = lcrold;
return dll;
}
//---------------------------------------
// UMOD_ReadDlh -
//---------------------------------------
UWORD8 UMOD_ReadDlh(UARTMOD_UartType_t UartType)
{
UWORD8 dlh, lcrold;
// DLL and DLH are accessible only when LCR[7]=1 or LCR=0xBF
//Store current value LCR and set it to 0xBF to access DLL
lcrold = UMOD_SetBfToLcr(UartType);
dlh = UARTMOD_DLH_REG(UartType);
//Restore LCR
UARTMOD_LCR_REG(UartType) = lcrold;
return dlh;
}
//----------------------------------------------------
// UMOD_ReadLsr
//----------------------------------------------------
UWORD8 UMOD_ReadLsr(UARTMOD_UartType_t UartType)
{
return UARTMOD_LSR_REG(UartType);
}
//------------------------------------------------
// UMOD_ReadMsr
//------------------------------------------------
UWORD8 UMOD_ReadMsr(UARTMOD_UartType_t UartType)
{
UWORD8 msrmodem,oldlcr,oldefr;
// clear lcr[7]
oldlcr = UMOD_ClearLcr7(UartType);
oldefr=UMOD_ClearEfr4(UartType);
msrmodem = UARTMOD_MSR_REG(UartType);
UMOD_RestoreEfr(oldefr,UartType);
//Restore LCR
UARTMOD_LCR_REG(UartType)= oldlcr;
return msrmodem;
}
//----------------------------------
// UMOD_ReadIsr
//----------------------------------
UWORD8 UMOD_ReadIsr(UARTMOD_UartType_t UartType)
{
return UARTMOD_ISR_REG(UartType);
}
//-----------------------------------
// UMOD_Read
//-----------------------------------
UWORD8 UMOD_Read(UARTMOD_UartType_t UartType)
{
return UARTMOD_RHR_REG(UartType) & 0xff;
}
//-----------------------------------------------
// UMOD_Send
//-----------------------------------------------
void UMOD_Send(const UWORD8 Value,UARTMOD_UartType_t UartType)
{
UARTMOD_THR_REG(UartType) = Value ;
}
//-----------------------------------------------------------------
// MODE DEFINITION REGISTER (MDR1)
//--------------------------------------------------------------------
UWORD8 UMOD_InitMdr1(const UARTMOD_SelectMode_t SelectMode,
const UARTMOD_SleepMode_t ir_sleep,
const UARTMOD_TXIRmode_t set_txir,
const UARTMOD_StartControlTrx_t sct,
const UARTMOD_SIPMode_t sip_mode,
const UARTMOD_FrameEndMode_t frame_end_mode,
const UARTMOD_UartType_t UartType)
{
UARTMOD_MDR1_REG(UartType) = SelectMode |
ir_sleep << 3 |
set_txir << 4 |
sct << 5 |
sip_mode << 6 |
frame_end_mode << 7;
return UARTMOD_MDR1_REG(UartType);
}
//--------------------------------
// UMOD_InitScr
//--------------------------------
UWORD8 UMOD_InitScr( const UARTMOD_DmaModeCtl_t DmaModeCtl,
const UARTMOD_DmaMode2_t DmaMode2,
const UARTMOD_TxEmptyCtrolIt_t TxEmptyCtrolIt,
const UARTMOD_RxCtsWakeupEnable_t RxCtsWakeupEnable,
const UARTMOD_DSR_It_t DsrIt,
const UARTMOD_Txtriggranu_t Txtriggranu,
const UARTMOD_Rxtriggranu_t Rxtriggranu,
UARTMOD_UartType_t UartType)
{
UWORD8 scr_modem;
UARTMOD_SCR_REG(UartType) = ( DmaModeCtl |
DmaMode2 << 1 |
TxEmptyCtrolIt << 3 |
RxCtsWakeupEnable << 4 |
DsrIt << 5 |
Txtriggranu << 6 |
Rxtriggranu <<7);
scr_modem = UARTMOD_SCR_REG(UartType);
return scr_modem;
}
//----------------------
// UMOD_SetFifoTrig
//
//this function allows the setting of Tx and Rx fifotrig at any level between 1 and 64
//
// SCR[6] (bit Txtriggranu has to be set to 1
// SCR[7] (bit Rxtriggranu has to be set to 1
// Tx and Rx triglevel LSB and MSB are loaded in FCR and TLR
//----------------------
UWORD8 UMOD_SetFifoTrig(UARTMOD_FifoEnable_t EnFifo ,
UARTMOD_RxFifoClear_t ClRxFifo,
UARTMOD_TxFifoClear_t ClTxFifo,
UARTMOD_DmaMode_t DmaMode,
UWORD8 TxTriggerFifoLevel,
UWORD8 RxTriggerFifoLevel,
UARTMOD_UartType_t UartType)
{
//enable SCR[6] (bit triggranu)
UARTMOD_SCR_REG(UartType)|=0x40;
//enable SCR[7] (bit triggranu)
UARTMOD_SCR_REG(UartType)|=0x80;
// load in FCR and TLR trig values
UMOD_InitTlr((UARTMOD_TxFifoTrigDma_t)(TxTriggerFifoLevel>>2),
(UARTMOD_RxFifoTrigDma_t)(RxTriggerFifoLevel>>2),
(UARTMOD_UartType_t)UartType);
UMOD_InitFcr(EnFifo,ClRxFifo,ClTxFifo,DmaMode,
(UARTMOD_TxFifoTrigger_t)(TxTriggerFifoLevel & 0x3),
(UARTMOD_RxFifoTrigger_t)(RxTriggerFifoLevel & 0x3),
(UARTMOD_UartType_t)UartType);
return((UWORD8)0);
}
//--------------------------------
// UMOD_InitTcr
//--------------------------------
UWORD8 UMOD_InitTcr(const UARTMOD_RxFifoTrigHalt_t trighalt,
const UARTMOD_RxFifoTrigStart_t trigstart,
UARTMOD_UartType_t UartType)
{
UWORD8 tcr_modem;
UWORD8 efr4,efr4old,mcr6old,lcrold;
//Store current value LCR and set it to 0xBF to access EFR
lcrold = UMOD_SetBfToLcr(UartType);
//store old value EFR register and Set EFR[4]=1
efr4old = UARTMOD_EFR_REG(UartType);
efr4 = efr4old | 0x10;
UARTMOD_EFR_REG(UartType) = efr4;
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