camcor.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

         {
             irqEventReg = 
               CAMCCC_IRQENABLESSC_ERR_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is False Synchronization Error */
    else if( intEvent == CAMCOR_FSC_ERR_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLEFSC_ERR_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLEFSC_ERR_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is Frame Height Error */
    else if( intEvent == CAMCOR_FW_ERR_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLEFW_ERR_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLEFW_ERR_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is FSP code error */
    else if( intEvent == CAMCOR_FSP_ERR_IRQ_EN )
    {
         /* TODO: enable this - no beach yet */
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             /*irqEventReg = 
               CAMCCC_IRQENABLEFSP_ERR_IRQ_ENSet32(irqEventReg, 1l);*/
         }
         else
         {
             /*irqEventReg = 
               CAMCCC_IRQENABLEFSP_ERR_IRQ_ENSet32(irqEventReg, 0l);*/
         }
    }
    /* check event is Frame End */
    else if( intEvent == CAMCOR_FE_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLEFE_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLEFE_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is Line Start */
    else if( intEvent == CAMCOR_LS_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLELS_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLELS_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is Line End */
    else if( intEvent == CAMCOR_LE_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLELE_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLELE_IRQ_ENSet32(irqEventReg, 0l);
         }
    }
    /* check event is Frame Frame Start */
    else if( intEvent == CAMCOR_FS_IRQ_EN )
    {
         /* check Mask OR Unmask */
         if ( maskUnmask )
         {   
             irqEventReg = 
               CAMCCC_IRQENABLEFS_IRQ_ENSet32(irqEventReg, 1l);
         }
         else
         {
             irqEventReg = 
               CAMCCC_IRQENABLEFS_IRQ_ENSet32(irqEventReg, 0l);
         }
    }

    CAMCCC_IRQENABLEWriteRegister32(baseAddress,irqEventReg);

    return returnCode; 
}


/*==================== Function Separator =============================*/

/*
-------------------------------------------------------------------------
        CAMCOR_IrqMaskAll
-------------------------------------------------------------------------
*/

ReturnCode_t CAMCOR_IrqMaskAll(
                      const UWORD32       baseAddress
                    )
{
    ReturnCode_t returnCode = TEST_OK;
   
    /*Check the input Parameters*/
    CHECK_INPUT_PARAM(baseAddress,0,RET_BAD_NULL_PARAM,RES_CAMCOR_BASE + RES_INVALID_INPUT_PARAM);

    CAMCCC_IRQENABLEWriteRegister32(baseAddress, 0);

    return returnCode; 
}                              

/*==================== Function Separator =============================*/

/*
-------------------------------------------------------------------------
        CAMCOR_ReadAckIrqStatus 
-------------------------------------------------------------------------
*/


ReturnCode_t CAMCOR_ReadAckIrqStatus(
                      const UWORD32              baseAddress,
                      const CAMCOR_IrqStatus_t   reqIrqStatus,
                      UWORD32 *const             pIrqStatus,
                      BOOL                       acknowledgeIrq
                    )
{
    ReturnCode_t returnCode = TEST_OK;
    UWORD32 irqStatus;
    UWORD32 irqStatusReg;
    UWORD32 irqAcknowledgeReg = 0;
   
   /*Check the input Parameters*/
    CHECK_INPUT_PARAM(baseAddress,0,RET_BAD_NULL_PARAM,RES_CAMCOR_BASE + RES_INVALID_INPUT_PARAM);

    /* read values from register */
    irqStatusReg = CAMCCC_IRQSTATUSReadRegister32(baseAddress);

    /* check event status is FIFO undeflow */
    if ( reqIrqStatus == CAMCOR_FIFO_UF_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFIFO_UF_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFIFO_UF_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is FIFO Overflow */
    else if( reqIrqStatus == CAMCOR_FIFO_OF_IRQ)
    {
        irqStatus = CAMCCC_IRQSTATUSFIFO_OF_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFIFO_OF_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* check event status is FIFO Threshold */
    else if( reqIrqStatus == CAMCOR_FIFO_THR_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFIFO_THR_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFIFO_THR_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is FIFO Full */
    else if( reqIrqStatus == CAMCOR_FIFO_FULL_IRQ)
    {
        irqStatus = CAMCCC_IRQSTATUSFIFO_FULL_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFIFO_FULL_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* check event status is FIFO No Empty */
    else if( reqIrqStatus == CAMCOR_FIFO_NOEMPTY_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is Shifted Synchronization error */
    else if( reqIrqStatus == CAMCOR_SSC_ERR_IRQ)
    {
        irqStatus = CAMCCC_IRQSTATUSSSC_ERR_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSSSC_ERR_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* check event status is Frame Synchronization Error */
    else if( reqIrqStatus == CAMCOR_FSC_ERR_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFSC_ERR_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFSC_ERR_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is Frame Height Error */
    else if( reqIrqStatus == CAMCOR_FW_ERR_IRQ)
    {
        irqStatus = CAMCCC_IRQSTATUSFW_ERR_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFW_ERR_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is FSP code error */
    else if( reqIrqStatus == CAMCOR_FSP_ERR_IRQ)
    {
        /* TODO: enable this - no beach yet */
        /*irqStatus = CAMCCC_IRQSTATUSFSP_ERR_IRQGet32(irqStatusReg);*/
        /*irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFSP_ERR_IRQSet32(irqAcknowledgeReg, 1l);*/
    }
    /* check event status is Frame End */
    else if( reqIrqStatus == CAMCOR_FE_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFE_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFE_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* check event status is Line Start */
    else if( reqIrqStatus == CAMCOR_LS_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSLS_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSLS_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* chk event status is Line End */
    else if( reqIrqStatus == CAMCOR_LE_IRQ)
    {
        irqStatus = CAMCCC_IRQSTATUSLE_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSLE_IRQSet32(irqAcknowledgeReg, 1l);
    }
    /* check event status is Frame Start */
    else if( reqIrqStatus == CAMCOR_FS_IRQ )
    {
        irqStatus = CAMCCC_IRQSTATUSFS_IRQGet32(irqStatusReg);
        irqAcknowledgeReg =
                 CAMCCC_IRQSTATUSFS_IRQSet32(irqAcknowledgeReg, 1l);
    }
    else
    {
        irqStatus = 0;
    }
    
    if(pIrqStatus != NULL)
    {
        *pIrqStatus = irqStatus;
    }
    
    if(acknowledgeIrq && irqStatus != 0)
    {
        CAMCCC_IRQSTATUSWriteRegister32(baseAddress, irqAcknowledgeReg);
    }

    return returnCode;
}

/*==================== Function Separator =============================*/

/*
-----------------------------------------------------------------------------
 NAME        : CAMCOR_CcpEnableDisable

-----------------------------------------------------------------------------
*/

ReturnCode_t CAMCOR_CcpEnableDisable(
                      const UWORD32            baseAddress,
                      const CAMCOR_SetClear_t  enableDisable
                    )
{ 
    ReturnCode_t returnCode = TEST_OK;
   
    /*Check the input Parameters*/
    CHECK_INPUT_PARAM(baseAddress,0,RET_BAD_NULL_PARAM,RES_CAMCOR_BASE + RES_INVALID_INPUT_PARAM);

    switch(enableDisable)
    {
        case CAMCOR_CLEAR:
            CAMCCC_CTRLCCP_MODEWrite32(baseAddress, CAMCOR_CLEAR);
        break;
        
        case CAMCOR_SET:
        default:
            CAMCCC_CTRLCCP_MODEWrite32(baseAddress, CAMCOR_SET);
        break;
    }
 
    return returnCode; 
}


/*==================== Function Separator =============================*/

/*
-----------------------------------------------------------------------------
 NAME        : CAMCOR_CcpConfigure

-----------------------------------------------------------------------------
*/