led_intvecs_a9.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
;
;   Property of Texas Instruments. For Unrestricted Internal Use Only.
;   Unauthorized reproduction and/or distribution is strictly prohibited.
;   This product is protected under copyright law and trade secret law
;   as an unpublished work.
;
;   Created 2002, (C) Copyright 2002 Texas Instruments.  All rights reserved.
;
;   Filename	: led_intvecs_a9.asm
;
;   Author	: Dayo Adeyeye, [e-mail]
;
;   Created	: 10th of October, 2002, 9.00am
;
;   Project	: Helen2. OMAP1610 Production DFT Led Exec code
;
;   Tools	: TI ARM tools, ARM926EJ-S
;
;   Description	: 
;		Declare interrupt/exception vector sections readonly
;		Declare entry and return label for interrupt handlers
;
;
;
;*******************************************************************************

	.state32
	
;; IMPORTED DATA/LABEL DECLARATION
	.global _c_int00		; IMPORT __main = prog_entry
	.global _EX_AbortD		; IMPORT _EX_AbortD
	.global	_EX_Irq			; IMPORT _EX_Irq
	.global	_EX_Fiq			; IMPORT _EX_Fiq
	.global $RES_Exception_LED		; IMPORT LED exception Handler
	
;; EXPORTED DATA/LABEL DECLARATION
	.global _reset			; EXPORT _reset
	.global ledINT_Swi		; EXPORT ledINT_Swi
	.global $ledINT_SetSupervisor	; EXPORT ledINT_SetSupervisor
	.global $ledINT_SetUser		; EXPORT ledINT_SetUser
	.global $ledINT_SetIRQBit	; EXPORT ledINT_SetIRQBit
	.global $ledINT_ClearIRQBit	; EXPORT ledINT_ClearIRQBit
	.global $ledINT_SetFIQBit	; EXPORT ledINT_SetFIQBit
	.global $ledINT_ClearFIQBit	; EXPORT ledINT_ClearFIQBit
	.global $DumpSPY_Results
	
;; DECLARE STACKS AREA, For TI tools stacks are allocated when needed.
	
;; INTERRUPT VECTORS SECTION START
;; Declare Interrupt vectors Branch Table code area
	.sect ".int_tbl"	; Sections code area for TI tools
	.state32
;; Interrupt Vectors Branch Table

_reset
	b	InitTest		; RESET INTERRUPT
undef_vector
	b	undef_handler		; UNDEFINED INSTRUCTION INTERRUPT
swi_vector
        ldr     pc, ledINT_SwiCall      ; SOFTWARE INTERRUPT HANDLER
abortI_vector
	b       abortI_handler		; ABORT (PREFETCH) INTERRUPT
abort_data_vector
	ldr     pc, _EX_AbortDCall      ;  ABORT (DATA) INT HANDLER
reserved_vector
	b	reserved_handler	; RESERVED
irq_vector
        ldr	pc, _EX_IrqCall         ; IRQ INTERRUPT HANDLER
fiq_vector
        ldr	pc, _EX_FiqCall         ; FIQ INTERRUPT HANDLER
	
;; Interrupt Vectors Handlers
undef_handler:
abortI_handler:
reserved_handler:
	str	lr, [sp]		; Save Undef LR b4 SVC mode
	mrs	r7, cpsr		; Take a copy of CPSR
	bic	r7,r7,#MODE_MASK	; Clear all mode bits
	orr	r7,r7,#SVC_MODE		; Set Supervisor Mode bits for CPSR
	msr	cpsr_all, r7		; Write back the modified CPSR
	add	r7, pc, #0x1
	bx	r7
	.state16		; Thumb state & supervisor mode for code density
	bl	$RES_Exception_LED
dump32mode:
        b	dump32mode
	
	.state32
;; DEFINE/VAR DECLARATION
	.align 4
ledINT_SwiCall		.word	ledINT_Swi
_EX_AbortDCall		.word	_EX_AbortD
_EX_IrqCall		.word	_EX_Irq
_EX_FiqCall		.word	_EX_Fiq
	
;; =============================================================================
;; =============================================================================
;; Thumb state Software Interrupt Handlers
	.state16
	.sect ".text"	; Named sections for code area
; $ledINT_SetSupervisor()
; Perform SWI to switch to supervisor mode
$ledINT_SetSupervisor
	mov	r3, lr
        swi	#0xFA         ; 0xFA : Enable ledINT_Swi
        mov	pc, r3   

; $ledINT_SetUser()
; Perform SWI to switch to User mode
$ledINT_SetUser:
	mov	r3, lr
        swi	#0xFB        ; 0xFB : Enable ledINT_Swi
	mov	pc, r3
	
; ledINT_SetIRQBit, Set IRQ bit of PSR (Program Status Register)
; (Disable IRQ)
$ledINT_SetIRQBit:
	mov	r3, lr
        swi	#0xF0		; 0xF0 : Set IRQ Bit of PSR
        mov	pc, r3
	
; ledINT_ClearIRQBit, Clear IRQ bit of PSR (Program Status Register)
; (Enable IRQ)
$ledINT_ClearIRQBit:
	mov	r3, lr
        swi	#0xF1		; 0xF1 : Clear IRQ Bit of PSR
        mov	pc, r3
	
; ledINT_SetFIQBit, Set FIQ bit of PSR (Program Status Register)
; (Disable FIQ)
$ledINT_SetFIQBit:
	mov	r3, lr
        swi	#0xF2		; 0xF2 : Set FIQ Bit of PSR
        mov	pc, r3

; ledINT_ClearFIQBit, Clear FIQ bit of PSR (Program Status Register)
; (Enable FIQ)
$ledINT_ClearFIQBit:
	mov	r3, lr
        swi	#0xF3		; 0xF3 : Clear FIQ Bit of PSR
        mov	pc, r3

;; =============================================================================
;; =============================================================================
	.state32
	.sect ".swint"	; Sections code area for TI tools
; Software Interrupt Vector Handlers
; ledINT_Swi(unsigned stack, unsigned stackSize)
;                  R0              R1
; Enable exception and set up a stack (Don't use R3)
; Works only if called from 16-bit (THUMB) mode
ledINT_Swi:
        ldrh	r4, [lr, #-2]		; retrieve SWI parameter
	and	r4, r4, #0xFF		; maskout all, keep argument only

        cmp	r4, #0xFB		; 0x1111_1011
        beq	SetUser			; Change to uP User mode
	
	cmp	r4, #0xFA		; 0x1111_1010
        beq	SetSupervisor		; Change to uP Supervisor mode

	cmp	r4, #0xF3		; 0x1111_0011
	beq	ClearFIQBit		; Enable FIQ Interrupt
	
	cmp	r4, #0xF2		; 0x1111_0010
	beq	SetFIQBit		; Disable FIQ interrupt
	
	cmp	r4, #0xF1		; 0x1111_0001
	beq	ClearIRQBit		; Enable IRQ Interrupt
	
	cmp	r4, #0xF0		; 0x1111_0000
	beq	SetIRQBit		; Disable IRQ interrupt
	
	b	ExitSwi			; not handled, Exit SWI

;; DEFINE/VAR DECLARATION	
IRQ_MASK	.equ     0x80	; IRQ mask value, bit 7.
FIQ_MASK	.equ     0x40	; FIQ mask value, bit 6
MODE_MASK	.equ     0x1F	; Processor Mode Mask bit 0 -> 4.
	
USR_MODE	.equ     0x10	; User Mode
FIQ_MODE	.equ     0x11	; Fast Interrupt Mode (FIQ)
IRQ_MODE	.equ     0x12	; Interrupt Mode (IRQ)
SVC_MODE	.equ     0x13	; Supervisor Mode
ABORT_MODE	.equ     0x17	; Abort Mode
UNDEF_MODE	.equ     0x1B	; Undefined Instruction Mode
SYSTEM_MODE	.equ     0x1F	; Privileged System User Mode

CLEAR_BIT	.equ     0x00	; Clear Bit
SET_BIT		.equ     0x01	; Set Bit
	
SetSupervisor:	
	mrs	r7, spsr		; Take a copy of Saved PSR
	bic	r7,r7,#MODE_MASK	; Clear all mode bits
	orr	r7,r7,#SVC_MODE		; Set Supervisor Mode bits for SPSR
	msr	SPSR, r7		; Write back the modified SPSR
	b	ExitSwi			; not handled

SetUser:
	mrs	r7, spsr		; Get copy of Saved PSR
	bic	r7,r7,#MODE_MASK	; Clear all mode bits
	orr	r7,r7,#USR_MODE		; Set User Mode bits for SPSR
	msr	SPSR,r7			; Write back the modified SPSR
	b	ExitSwi			; not handled
	
SetIRQBit:
	mov	r5, #IRQ_MASK
        mov	r6, #SET_BIT
	b	SetClearFIQIRQ

ClearIRQBit:
	mov	r5, #IRQ_MASK
        mov	r6, #CLEAR_BIT
	b	SetClearFIQIRQ

SetFIQBit:
	mov	r5, #FIQ_MASK
        mov	r6, #SET_BIT
	b	SetClearFIQIRQ

ClearFIQBit:
	mov	r5, #FIQ_MASK
        mov	r6, #CLEAR_BIT
	b	SetClearFIQIRQ

SetClearFIQIRQ:
	mrs	r7, SPSR        ; read saved PSR
	bic	r7, r7, r5      ; clear FIQ or IRQ bit of saved PSR
	cmp	r6, #CLEAR_BIT  ; Test if to CLEAR or SET INTERRUPT Bits
	beq	STORE_SPSR      ; do not set any bit of saved PSR
	orr	r7, r7, r5      ; set FIQ or IRQ bit of saved PSR
STORE_SPSR:
	msr	SPSR, r7	; store saved PSR to set or clear FIQ or IRQ bit

ExitSwi:
	movs	pc, lr           ; return from SWI, ldr pc, =lr
	

;; ====================================================================
;; ====================================================================
;; Execution BOOT CODE SECTION START
	.state32
	.sect ".execled"	; RESET  code area for TI tools
InitTest:
	;;  ARM 32bit State
; Basic Initializations and Testmode detection
	
	;;  Thumb 16bit State
; Sets up SVC Supervisor STACK = 0x20000A00
; Sets up Undefined Instruction stack = 0x20000144
; Sets up DATA ABORT stack = 0x20000804
; Sets up FIQ stack and enable FIQ = 0x20000900
; Sets up IRQ stack and enable IRQ = 0x200001C0
	
	;;  ARM 32bit State
; Flush & Invalidate all Icache & Dcache
; Flush & Invalidate all TLB
; Enable Instruction Cache Only
	
	;;  Thumb 16bit State
; Releases ARMPERRST
	;; No Spy dump issues here as ULPD and DPLL are in bypass mode
; Sets ULPD to 19.2MHz instead of 12MHz, with 64*6 = 384 clk cycles timeout.
; Enable and Set DPLL to CK_REF, with 64 * 6 = 384 clk cycles timeout.

; EMIFF setups are not applicable to Helen2 LED DFT
	
; Enables all Idle select and wakeup
; Enables ARMPERCK and ARMXORCK, LCDCK, APICK and no DPLL OUT
; Enables T1CK and idle
	
; Store BOOTROM TLB MMU Translation Table in TestSRAM (Re-mapped later for Test)
; Store SPY Space TLB MMU Translation Table in TestSRAM
; Store FLASH Address TLB MMU Translation Table in TestSRAM
; Store TestSRAM Address TLB MMU Translation Table in TestSRAM
; Store all OMAP Rhea Address TLB MMU Translation Table in TestSRAM
	
; Enable abort generation on ARM public and private Rhea bridge
; Configure DMA for LCD reset only (TBD)
; Initialize/Reset to zero ARM926EJ-S internal registers.

	;;  ARM 32bit State
; Write TTB value to register = 0x20000000
; Write ARM WR DOMAIN Access permission REG
; Write Enable MMU and Dchache together
; Check User JTAG for atspeed test and Setup CFG initialization
	
	;;  Thumb 16bit State in C code
; Reset mode 1. 1st config hel2 IO's for non-multiplexed Address & GPIO with correct up/down's.
; Reset mode 0. No need to Configure EMIFS and GPIO IO pads
; Configure EMIFS CS1 & CS2 Async access and CS3 burst synchronous.
	
	;;  Thumb-ARM-Thumb 16bit State in C code
; Store CTE values in TESTSRAM CTE Space
; Test if the emifs configurration CTE parameter is set to 7, if set, config
; Reset the Helen2 Level 2 Interrupt control handlers.
; Setup gpio pins and registers from CTE parameters. (edge, execute and sync)
; Initialize and interrupt Sync pin handler from CTE parameter.
; Set Supervisor mode.
; Put ARM9 in Big Sleep idle mode and wait for GPIO sync pin interrupt.
; Set User mode.

	;; DMA download for MGS3+ and ARM926
;
;
	
; Remap TLB MMU Translation Table in TestSRAM for virtual address 0x0 to 0x2ffc

	;; INT_EndOfLoad(gpio_base_addr, execpin)
; Drain ARM926 Data Cache Write buffer
; Test, Clean and Invalidate all ARM926 Data cache, very important
; Disable ARM926 MMU, Dcache and Icache.
; Flush the instruction & Data cache and Invalidate all TLB.
; Re-enable Enable ARM MMU, Icache, Dcache and Alignment
	
; Write Enable MMU, Dchache and Ichache together first
        mrc	p15, #0, r0, c1, c0	; Read I-cache CP15 Co-pro control reg.
	bic	r0, r0, #0x2		; Clear bit
	; Disable Data Address Alignment fault checker in MMU for OMAP3.2 LED.
        mcr	p15, #0, r0, c1, c0	; Enable (I & D) Cache & MMU

	
; Jump to start address in TESTSRAM, which starts here
	
; clock tree initialization
; Set the synchronous scalable mode from fully synchronous mode
; Set clock divider: ARM=DSP=LCD run at DPLL1 freq, TC=PERI runs at DPLL/2.
; Enable the DSP_CK activation during reset, ARM inth run at ARM/2 clk.
; Sets DPLL ratio
	
;; ==============================================================================
;; HELEN2 OMAP1610 DFT LED code execution start here
	ldr	r0, prog_entry  ; load C handler address for LED BOOT
	mov	pc, r0   ; C routine RESET INTERRUPT
	
;; ==============================================================================
	.state32
prog_entry		.word	_c_int00

	
;; ============== DO NOT REMOVE ======= USE FOR TDL GENERATION =================
	.state16
	.sect ".exitsim"
;===============================================================================
; $DumpSPY_Results()
;     gpio_base_addr   ------> R0
;     statuspin        ------> R1
;
; Input  : r0 = gpio base address. r1 = gpio Status pin. 
; Output : None.
;	The spy result location size is fixed at 256 bytes.
;===============================================================================
$DumpSPY_Results:
	ldr	r2, SPY_SPACE   ; Ptr to spy result mem location is in r2
	ldr	r7, [r2]   ; r7 contains pointer to first spy result
	ldr	r6, SPY_OUTPUT  ; r6 contains pointer to spy component
        ; Stores error count in r4
	ldrh	r4, [r7, #4]   ; spy pointer+2 as 1st & 2nd outputs are 5555, AAAA
        ;; Set the global result of the test on STATUS_PIN gpio(4) 1=OK or 0=fail
	mov	r5, #0x0	; Sets r5 to zero
	cmp	r4, #0		; If r4 == 0 (no error count)
	bne	dump_start
	mov	r5, #0x1	; Sets r5 to one
	lsl	r5, r1		; Sets r5 STATUS_PIN gpio(4) bit to one
dump_start: 	
	; Now r5 contains the value to be loaded at the address pointed by r0
	; Loops until spy last address is reached
	ldr	r3, SPY_END	; r3 contains F1F1 (last spy value)
	b	loopstart	; Loops
dump_loop:                       
	strh	r2, [r6]	; Puts r2 content into addr pnted by r6
	add	r7, #0x2	; r7 is incrd, r7 points to next spy value
	add	r6, #0x2	; r6 is incremented
loopstart:			; r2 = 1st (0x5555) spy value
	ldrh	r2, [r7]	; Stores into r2 address pointer by r7
	cmp	r2, r3		; If r2 != F1F1
	bne	dump_loop	; Loops
	; Set the Status pin and Writes 0xFFFF to spy to end simulation
	ldr	r7, SPY_ENDSPACE
	ldr	r6, SPY_STOP
	add	r0, #0x30	; r0 contains ptr on GPIO out space
	strh	r5, [r0]	; Sets GPIO_2 to its correct value
	strh	r6, [r7]	; Actually writes 0xFFFF
wait_forever:
	b	wait_forever

; DEFINE/VAR DECLARATION or DATA/LABEL DECLARATION
SPY_SPACE	.word	0x20000040
SPY_OUTPUT	.word	0x05000000
SPY_ENDSPACE	.word	0x050000FE
SPY_STOP	.word	0xFFFF
SPY_DATA	.word	0x5555
SPY_FAIL	.word	0xDEAD
SPY_END	.word	0xF1F1

	.end			; Terminate assembly