📄 camc1regtst.c
字号:
0xffffffff,
0xff000003,
0xffffffff,
0x0,
0xffffffff,
ACC_32BIT},
/* register: CC_CCPLSCR in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_CCPLSCR_ID,
CAMC1_CC_CCPLSCR_OFFSET,
0xffffffff,
0xff000000,
0xffffffff,
0x0,
0xffffffff,
ACC_32BIT},
/* register: CC_CCPLECR in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_CCPLECR_ID,
CAMC1_CC_CCPLECR_OFFSET,
0xffffffff,
0xff000001,
0xffffffff,
0x0,
0xffffffff,
ACC_32BIT},
/* register: CC_CCPDFR in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_CCPDFR_ID,
CAMC1_CC_CCPDFR_OFFSET,
0xff0f,
0x0,
0xffffffff,
0x0,
0xff0f,
ACC_32BIT}
};
const registerROWOStruct CAMC1RegisterROData[CAMC1_RO_REGISTERS] =
{
/* register: CC_REVISION in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_REVISION_ID,
CAMC1_CC_REVISION_OFFSET,
0xff,
0x10,
0xffffffff,
0x0,
0xff,
ACC_32BIT},
/* register: CC_SYSSTATUS in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_SYSSTATUS_ID,
CAMC1_CC_SYSSTATUS_OFFSET,
0x1,
0x0,
0xffffffff,
0x0,
0x1,
ACC_32BIT},
/* register: CC_CTRL_DMA in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_CTRL_DMA_ID,
CAMC1_CC_CTRL_DMA_OFFSET,
0x0,
0x107,
0xffffffff,
0x0,
0x17f,
ACC_32BIT},
/* register: CC_TEST in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_TEST_ID,
CAMC1_CC_TEST_OFFSET,
0xffffffff,
0x0,
0xffffffff,
0x0,
0xffffffff,
ACC_32BIT},
/* register: CC_GENPAR in cell: CAMC1 */ { CAMC1_BASE_ID + CAMC1_CC_GENPAR_ID,
CAMC1_CC_GENPAR_OFFSET,
0x7,
0x6,
0xffffffff,
0x0,
0x7,
ACC_32BIT}
};
/*****************************************************************************
* LOCAL VARIABLES DECLARATIONS
******************************************************************************
*/
/*****************************************************************************
* LOCAL FUNCTIONS PROTOTYPES
******************************************************************************
*/
/*****************************************************************************
* FUNCTIONS
******************************************************************************
*/
void CAMC1PowerOnResetTest(const UWORD32 baseAddress)
{
UWORD32 i;
UWORD32 regVal32;
UWORD16 regVal16;
UWORD8 regVal8;
MSG_START_POR_TESTS;
for( i = 0 ; i < CAMC1_POR_REGISTERS ; i++ )
{
switch( CAMC1PowerOnResetData[i].regType )
{
case ACC_32BIT:
{
regVal32 = RD_MEM_32_VOLATILE(CAMC1PowerOnResetData[i].address + baseAddress);
MSG_POR_TEST(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address);
regVal32 &= CAMC1PowerOnResetData[i].powerOnMask;
// Check value of register
if( regVal32 != (((CAMC1PowerOnResetData[i].powerOnValue & CAMC1PowerOnResetData[i].rsrvdReturnZerosMask) | CAMC1PowerOnResetData[i].rsrvdReturnOnesMask) & CAMC1PowerOnResetData[i].powerOnMask))
{
MSG_POR_FAIL(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address, regVal32);
}
break;
}
case ACC_16BIT:
{
regVal16 = RD_MEM_16_VOLATILE(CAMC1PowerOnResetData[i].address + baseAddress);
MSG_POR_TEST(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address);
regVal16 &= CAMC1PowerOnResetData[i].powerOnMask;
// Check value of register
if( regVal16 != (((CAMC1PowerOnResetData[i].powerOnValue & CAMC1PowerOnResetData[i].rsrvdReturnZerosMask) | CAMC1PowerOnResetData[i].rsrvdReturnOnesMask) & CAMC1PowerOnResetData[i].powerOnMask))
{
MSG_POR_FAIL(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address, regVal16);
}
break;
}
case ACC_8BIT:
{
regVal8 = RD_MEM_8_VOLATILE(CAMC1PowerOnResetData[i].address + baseAddress);
MSG_POR_TEST(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address);
regVal8 &= CAMC1PowerOnResetData[i].powerOnMask;
// Check value of register
if( regVal8 != (((CAMC1PowerOnResetData[i].powerOnValue & CAMC1PowerOnResetData[i].rsrvdReturnZerosMask) | CAMC1PowerOnResetData[i].rsrvdReturnOnesMask) & CAMC1PowerOnResetData[i].powerOnMask))
{
MSG_POR_FAIL(CAMC1PowerOnResetData[i].regType, CAMC1PowerOnResetData[i].address, regVal8);
}
break;
}
default:
break;
}
}
MSG_END_POR_TESTS;
}
void CAMC1RegisterExclusivityTestUp(const UWORD32 baseAddress)
{
UWORD32 i;
UWORD32 regVal;
registerExclusivityStruct r;
UWORD32 ONES32;
UWORD32 ZEROS32;
UWORD16 ONES16;
UWORD16 ZEROS16;
UWORD8 ONES8;
UWORD8 ZEROS8;
MSG_START_RE_UP_TESTS;
for( i = 0 ; i < CAMC1_EXCLUSIVITY_REGISTERS ; i++ )
{
r = CAMC1RegisterExclusivityData[i];
MSG_RE_UP_TEST_PART1(r.regType, r.address);
ONES32 = (0xffffffff & r.includeMask) | (r.powerOnValue & ~r.includeMask);
ZEROS32 = r.powerOnValue & ~r.includeMask;
ONES16 = (0xffff & (UWORD16)r.includeMask) | ((UWORD16)r.powerOnValue & ~(UWORD16)r.includeMask);
ZEROS16 = (UWORD16)r.powerOnValue & ~(UWORD16)r.includeMask;
ONES8 = (0xff & (UWORD8)r.includeMask) | ((UWORD8)r.powerOnValue & ~(UWORD8)r.includeMask);
ZEROS8 = (UWORD8)r.powerOnValue & ~(UWORD8)r.includeMask;
switch( r.regType )
{
case ACC_32BIT:
{
if( (READ_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
regVal = RD_MEM_32_VOLATILE(r.address + baseAddress);
if( (regVal & r.powerOnMask) != (((r.powerOnValue & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.powerOnMask))
{
MSG_RE_UP_POWER_ON_FAIL(r.regType, r.address, regVal);
}
}
if( (WRITE_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
WR_MEM_32_VOLATILE(r.address + baseAddress, ONES32);
}
if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_32_VOLATILE(r.address + baseAddress);
if( (((ONES32 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.readMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ONES_FAIL(r.regType, r.address, regVal);
}
}
break;
}
case ACC_16BIT:
{
if( (READ_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
regVal = RD_MEM_16_VOLATILE(r.address + baseAddress);
if( (regVal & r.powerOnMask) != (((r.powerOnValue & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.powerOnMask))
{
MSG_RE_UP_POWER_ON_FAIL(r.regType, r.address, regVal);
}
}
if( (WRITE_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
WR_MEM_16_VOLATILE(r.address + baseAddress, ONES16);
}
if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_16_VOLATILE(r.address + baseAddress);
if( (((ONES16 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.readMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ONES_FAIL(r.regType, r.address, regVal);
}
}
break;
}
case ACC_8BIT:
{
if( (READ_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
regVal = RD_MEM_8_VOLATILE(r.address + baseAddress);
if( (regVal & r.powerOnMask) != (((r.powerOnValue & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.powerOnMask))
{
MSG_RE_UP_POWER_ON_FAIL(r.regType, r.address, regVal);
}
}
if( (WRITE_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
WR_MEM_8_VOLATILE(r.address + baseAddress, ONES8);
}
if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_8_VOLATILE(r.address + baseAddress);
if( (((ONES8 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.readMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ONES_FAIL(r.regType, r.address, regVal);
}
}
break;
}
default:
break;
}
}
for( i = 0 ; i < CAMC1_EXCLUSIVITY_REGISTERS ; i++ )
{
r = CAMC1RegisterExclusivityData[i];
MSG_RE_UP_TEST_PART2(r.regType, r.address);
ONES32 = (0xffffffff & r.includeMask) | (r.powerOnValue & ~r.includeMask);
ZEROS32 = r.powerOnValue & ~r.includeMask;
ONES16 = (0xffff & (UWORD16)r.includeMask) | ((UWORD16)r.powerOnValue & ~(UWORD16)r.includeMask);
ZEROS16 = (UWORD16)r.powerOnValue & ~(UWORD16)r.includeMask;
ONES8 = (0xff & (UWORD8)r.includeMask) | ((UWORD8)r.powerOnValue & ~(UWORD8)r.includeMask);
ZEROS8 = (UWORD8)r.powerOnValue & ~(UWORD8)r.includeMask;
switch( r.regType )
{
case ACC_32BIT:
{
if( READ_ONLY == r.IOstatus )
{
regVal = RD_MEM_32_VOLATILE(r.address + baseAddress);
if( (regVal & r.powerOnMask) != (((r.powerOnValue & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.powerOnMask))
{
MSG_RE_UP_POWER_ON_FAIL(r.regType, r.address, regVal);
}
}
else if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_32_VOLATILE(r.address + baseAddress);
if( (((ONES32 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.readMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ONES_FAIL(r.regType, r.address, regVal);
}
}
if( (WRITE_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
{
WR_MEM_32_VOLATILE(r.address + baseAddress, ZEROS32);
}
if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_32_VOLATILE(r.address + baseAddress);
if( ((ZEROS32 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ZEROS_FAIL(r.regType, r.address, regVal);
}
}
break;
}
case ACC_16BIT:
{
if( READ_ONLY == r.IOstatus )
{
regVal = RD_MEM_16_VOLATILE(r.address + baseAddress);
if( (regVal & r.powerOnMask) != (((r.powerOnValue & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.powerOnMask))
{
MSG_RE_UP_POWER_ON_FAIL(r.regType, r.address, regVal);
}
}
else if( READ_WRITE == r.IOstatus )
{
regVal = RD_MEM_16_VOLATILE(r.address + baseAddress);
if( (((ONES16 & r.rsrvdReturnZerosMask) | r.rsrvdReturnOnesMask) & r.readMask) != (regVal & r.readMask) )
{
MSG_RE_UP_ONES_FAIL(r.regType, r.address, regVal);
}
}
if( (WRITE_ONLY == r.IOstatus) || (READ_WRITE == r.IOstatus) )
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