📄 elcd.c
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RW_TEST_READ(ELCD_TE_REG,VS_COUNTER,32);
RW_TEST_READ(ELCD_TE_REG,TE_INVERTED,32);
RW_TEST_READ(ELCD_TE_REG,MODE,32);
RW_TEST_READ(ELCD_TE_REG,HS_MATCH,32);
RW_TEST_READ(ELCD_TE_REG,VS_DETECT,32);
RW_TEST_READ(ELCD_TE_REG,PULSE_DETECT,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_TE_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_ELCDCTL_REG,32);
// RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,SWAP_DISABLE,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,BUS_SIZE,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,RX_PACKING,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,UNUSUED_BITS,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,NCYCLE,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,NDUMMY,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,ELCD_NRESET,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,ELCD_DNC,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,ELCD_NCS1,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,ELCD_NCS0,32);
RW_WRITE(ELCD_ELCDCTL_REG);
// RW_TEST_READ(ELCD_ELCDCTL_REG,RESERVED,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,SWAP_DISABLE,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,BUS_SIZE,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,RX_PACKING,32);
RW_PREPARE_WRITE(ELCD_ELCDCTL_REG,UNUSUED_BITS,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,NCYCLE,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,NDUMMY,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,ELCD_NRESET,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,ELCD_DNC,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,ELCD_NCS1,32);
RW_TEST_READ(ELCD_ELCDCTL_REG,ELCD_NCS0,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_ELCDCTL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CMDTX_REG,32);
// RW_PREPARE_WRITE(ELCD_CMDTX_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CMDTX_REG,CMD,32);
RW_WRITE(ELCD_CMDTX_REG);
// RW_TEST_READ(ELCD_CMDTX_REG,RESERVED,32);
RW_TEST_READ(ELCD_CMDTX_REG,CMD,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CMDTX_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_COUNTERRX_REG,32);
// RW_PREPARE_WRITE(ELCD_COUNTERRX_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_COUNTERRX_REG,COUNTERRX,32);
RW_WRITE(ELCD_COUNTERRX_REG);
// RW_TEST_READ(ELCD_COUNTERRX_REG,RESERVED,32);
RW_TEST_READ(ELCD_COUNTERRX_REG,COUNTERRX,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_COUNTERRX_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_PIXELPOS_REG,32);
// RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,PIXEL_SIZE,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,NPIXELS,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,PIX4_RP,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,PIX3_RP,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,PIX2_RP,32);
RW_PREPARE_WRITE(ELCD_PIXELPOS_REG,PIX1_RP,32);
RW_WRITE(ELCD_PIXELPOS_REG);
// RW_TEST_READ(ELCD_PIXELPOS_REG,RESERVED,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,PIXEL_SIZE,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,NPIXELS,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,PIX4_RP,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,PIX3_RP,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,PIX2_RP,32);
RW_TEST_READ(ELCD_PIXELPOS_REG,PIX1_RP,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_PIXELPOS_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE1_REG1,32);
// RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_4_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_4,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_3_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_3,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_2_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_2,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_1_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_1,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_0_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG1,CYCLE1_0,32);
RW_WRITE(ELCD_CYCLE1_REG1);
// RW_TEST_READ(ELCD_CYCLE1_REG1,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_4_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_4,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_3_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_3,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_2_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_2,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_1_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_1,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_0_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG1,CYCLE1_0,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE1_REG1);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE1_REG2,32);
// RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_9_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_9,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_8_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_8,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_7_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_7,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_6_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_6,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_5_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG2,CYCLE1_5,32);
RW_WRITE(ELCD_CYCLE1_REG2);
// RW_TEST_READ(ELCD_CYCLE1_REG2,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_9_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_9,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_8_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_8,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_7_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_7,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_6_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_6,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_5_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG2,CYCLE1_5,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE1_REG2);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE1_REG3,32);
// RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_14_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_14,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_13_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_13,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_12_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_12,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_11_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_11,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_10_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG3,CYCLE1_10,32);
RW_WRITE(ELCD_CYCLE1_REG3);
// RW_TEST_READ(ELCD_CYCLE1_REG3,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_14_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_14,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_13_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_13,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_12_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_12,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_11_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_11,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_10_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG3,CYCLE1_10,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE1_REG3);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE1_REG4,32);
// RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_19_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_19,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_18_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_18,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_17_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_17,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_16_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_16,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_15_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG4,CYCLE1_15,32);
RW_WRITE(ELCD_CYCLE1_REG4);
// RW_TEST_READ(ELCD_CYCLE1_REG4,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_19_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_19,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_18_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_18,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_17_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_17,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_16_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_16,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_15_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG4,CYCLE1_15,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE1_REG4);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE1_REG5,32);
// RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_23_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_23,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_22_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_22,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_21_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_21,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_20_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE1_REG5,CYCLE1_20,32);
RW_WRITE(ELCD_CYCLE1_REG5);
// RW_TEST_READ(ELCD_CYCLE1_REG5,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_23_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_23,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_22_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_22,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_21_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_21,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_20_STS,32);
RW_TEST_READ(ELCD_CYCLE1_REG5,CYCLE1_20,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE1_REG5);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE2_REG1,32);
// RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_4_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_4,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_3_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_3,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_2_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_2,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_1_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_1,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_0_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG1,CYCLE2_0,32);
RW_WRITE(ELCD_CYCLE2_REG1);
// RW_TEST_READ(ELCD_CYCLE2_REG1,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_4_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_4,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_3_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_3,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_2_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_2,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_1_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_1,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_0_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG1,CYCLE2_0,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE2_REG1);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE2_REG2,32);
// RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_9_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_9,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_8_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_8,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_7_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_7,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_6_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_6,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_5_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG2,CYCLE2_5,32);
RW_WRITE(ELCD_CYCLE2_REG2);
// RW_TEST_READ(ELCD_CYCLE2_REG2,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_9_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_9,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_8_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_8,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_7_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_7,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_6_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_6,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_5_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG2,CYCLE2_5,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE2_REG2);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE2_REG3,32);
// RW_PREPARE_WRITE(ELCD_CYCLE2_REG3,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG3,CYCLE2_11_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG3,CYCLE2_11,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG3,CYCLE2_10_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE2_REG3,CYCLE2_10,32);
RW_WRITE(ELCD_CYCLE2_REG3);
// RW_TEST_READ(ELCD_CYCLE2_REG3,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE2_REG3,CYCLE2_11_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG3,CYCLE2_11,32);
RW_TEST_READ(ELCD_CYCLE2_REG3,CYCLE2_10_STS,32);
RW_TEST_READ(ELCD_CYCLE2_REG3,CYCLE2_10,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE2_REG3);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE3_REG1,32);
// RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_4_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_4,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_3_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_3,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_2_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_2,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_1_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_1,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_0_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG1,CYCLE3_0,32);
RW_WRITE(ELCD_CYCLE3_REG1);
// RW_TEST_READ(ELCD_CYCLE3_REG1,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_4_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_4,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_3_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_3,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_2_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_2,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_1_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_1,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_0_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG1,CYCLE3_0,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE3_REG1);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_CYCLE3_REG2,32);
// RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_7_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_7,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_6_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_6,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_5_STS,32);
RW_PREPARE_WRITE(ELCD_CYCLE3_REG2,CYCLE3_5,32);
RW_WRITE(ELCD_CYCLE3_REG2);
// RW_TEST_READ(ELCD_CYCLE3_REG2,RESERVED,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_7_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_7,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_6_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_6,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_5_STS,32);
RW_TEST_READ(ELCD_CYCLE3_REG2,CYCLE3_5,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CYCLE3_REG2);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_COUNTERTX_REG,32);
RW_PREPARE_WRITE(ELCD_COUNTERTX_REG,COUNTERTX,32);
RW_WRITE(ELCD_COUNTERTX_REG);
RW_TEST_READ(ELCD_COUNTERTX_REG,COUNTERTX,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_COUNTERTX_REG);
END_RW_TEST();
END_ACCESS_MODULE();
}
//---------------------------------------------------------
//NAME : ELCD_SoftReset
//DESCRIPTION : To perform an ELCD soft reset
//PARAMETERS :
//RETURN VALUE:
//LIMITATIONS :
//---------------------------------------------------------
void ELCD_SoftReset(void){
SetGroupBits32(ELCD_CONTROL_REG, ELCD_CONTROL_REG_SOFT_RESET_POS, ELCD_CONTROL_REG_SOFT_RESET_NUMB, 1);
SetGroupBits32(ELCD_CONTROL_REG, ELCD_CONTROL_REG_SOFT_RESET_POS, ELCD_CONTROL_REG_SOFT_RESET_NUMB, 0);
}
//---------------------------------------------------------
//NAME : ELCD_SelectMode
//DESCRIPTION : To select a bus mode between Motorola 6800 & Intel 8086
//PARAMETERS : mode can be either MOTOROLA_6800 or INTEL_8086
//RETURN VALUE:
//LIMITATIONS :
//---------------------------------------------------------
void ELCD_SelectMode(ELCD_mode_t mode){
SetGroupBits32(ELCD_CONTROL_REG, ELCD_CONTROL_REG_MODE_POS, ELCD_CONTROL_REG_MODE_NUMB, mode);
}
//---------------------------------------------------------
//NAME : ELCD_SetReadOnPolarity
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