📄 elcd.c
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
// Filename : elcd.c
// Date of Module Modification:1/7/04
// Date of Generation :1/7/04
//
// Yoan Hebrard (y-hebrard@ti.com)
//
//===============================================================================
#include "global_types.h"
#include "elcd.h"
#include "testaccess.h"
#include "error.h"
//---------------------------------------------------------------------
// NAME : ELCD_TestResetValue
//
// DESCRIPTION : Test the reset values of ELCD registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ELCD_Test_ResetValue(void)
{
BEGIN_RESET_MODULE();
BEGIN_RESET_TEST(ELCD_CONTROL_REG,32);
TEST_FIELD_RESET(ELCD_CONTROL_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_CONTROL_REG,DMALCD_WU,32);
TEST_FIELD_RESET(ELCD_CONTROL_REG,MODE,32);
TEST_FIELD_RESET(ELCD_CONTROL_REG,POWER_SAVING,32);
TEST_FIELD_RESET(ELCD_CONTROL_REG,SOFT_RESET,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_ONOFFTIME_REG,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,PRESCALER,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,RON_POLARITY,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,WON_POLARITY,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,WEDGE,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,READ_OFF,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,READ_ON,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,WRITE_OFF,32);
TEST_FIELD_RESET(ELCD_ONOFFTIME_REG,WRITE_ON,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_DMAIT_REG,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,RXFIFO_THRESHOLD,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,TXFIFO_THRESHOLD,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,IT_RX_EN,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,IT_TX_EN,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,DMA_RX_EN,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,DMA_TX_EN,32);
TEST_FIELD_RESET(ELCD_DMAIT_REG,TX_MODE,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_TE_REG,32);
TEST_FIELD_RESET(ELCD_TE_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_TE_REG,VS_COUNTER,32);
TEST_FIELD_RESET(ELCD_TE_REG,TE_INVERTED,32);
TEST_FIELD_RESET(ELCD_TE_REG,MODE,32);
TEST_FIELD_RESET(ELCD_TE_REG,HS_MATCH,32);
TEST_FIELD_RESET(ELCD_TE_REG,VS_DETECT,32);
TEST_FIELD_RESET(ELCD_TE_REG,PULSE_DETECT,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_ELCDCTL_REG,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,SWAP_DISABLE,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,BUS_SIZE,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,RX_PACKING,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,UNUSUED_BITS,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,NCYCLE,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,NDUMMY,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,ELCD_NRESET,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,ELCD_DNC,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,ELCD_NCS1,32);
TEST_FIELD_RESET(ELCD_ELCDCTL_REG,ELCD_NCS0,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CMDTX_REG,32);
TEST_FIELD_RESET(ELCD_CMDTX_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_CMDTX_REG,CMD,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_DATATX_REG,32);
TEST_FIELD_RESET(ELCD_DATATX_REG,TXDATA,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_COUNTERRX_REG,32);
TEST_FIELD_RESET(ELCD_COUNTERRX_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_COUNTERRX_REG,COUNTERRX,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_DATARX_REG,32);
TEST_FIELD_RESET(ELCD_DATARX_REG,DATARX,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_STATUS_REG,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,IDLE,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,CMDTX_END,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,WRITE_END,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,READ_END,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,RXFIFOFULL,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,RXFIFOEMPTY,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,TXFIFOFULL,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,TXFIFOEMPTY,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,IT_TX,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,IT_RX,32);
TEST_FIELD_RESET(ELCD_STATUS_REG,RESET_DONE,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_PIXELPOS_REG,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,PIXEL_SIZE,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,NPIXELS,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,PIX4_RP,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,PIX3_RP,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,PIX2_RP,32);
TEST_FIELD_RESET(ELCD_PIXELPOS_REG,PIX1_RP,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE1_REG1,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_4_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_4,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_3_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_3,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_2_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_2,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_1_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_1,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_0_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG1,CYCLE1_0,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE1_REG2,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_9_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_9,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_8_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_8,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_7_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_7,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_6_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_6,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_5_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG2,CYCLE1_5,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE1_REG3,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_14_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_14,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_13_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_13,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_12_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_12,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_11_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_11,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_10_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG3,CYCLE1_10,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE1_REG4,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_19_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_19,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_18_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_18,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_17_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_17,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_16_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_16,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_15_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG4,CYCLE1_15,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE1_REG5,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_23_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_23,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_22_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_22,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_21_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_21,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_20_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE1_REG5,CYCLE1_20,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE2_REG1,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_4_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_4,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_3_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_3,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_2_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_2,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_1_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_1,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_0_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG1,CYCLE2_0,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE2_REG2,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_9_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_9,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_8_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_8,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_7_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_7,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_6_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_6,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_5_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG2,CYCLE2_5,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE2_REG3,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG3,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG3,CYCLE2_11_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG3,CYCLE2_11,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG3,CYCLE2_10_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE2_REG3,CYCLE2_10,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE3_REG1,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_4_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_4,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_3_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_3,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_2_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_2,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_1_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_1,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_0_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG1,CYCLE3_0,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_CYCLE3_REG2,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,RESERVED,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_7_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_7,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_6_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_6,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_5_STS,32);
TEST_FIELD_RESET(ELCD_CYCLE3_REG2,CYCLE3_5,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_REVNB_REG,32);
TEST_FIELD_RESET(ELCD_REVNB_REG,RESERVED,32);
TEST_FIELD_RESET(ELCD_REVNB_REG,MSB_REVNB,32);
TEST_FIELD_RESET(ELCD_REVNB_REG,LSB_REVNB,32);
END_RESET_TEST();
BEGIN_RESET_TEST(ELCD_COUNTERTX_REG,32);
TEST_FIELD_RESET(ELCD_COUNTERTX_REG,COUNTERTX,32);
END_RESET_TEST();
END_RESET_MODULE();
}
//---------------------------------------------------------------------
// NAME : ELCD_TestRegistersAccess
//
// DESCRIPTION : Test the access to ELCD registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ELCD_TestRegistersAccess(void)
{
BEGIN_ACCESS_MODULE();
BEGIN_RW_TEST(ELCD_CONTROL_REG,32);
//RW_PREPARE_WRITE(ELCD_CONTROL_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_CONTROL_REG,DMALCD_WU,32);
RW_PREPARE_WRITE(ELCD_CONTROL_REG,MODE,32);
RW_PREPARE_WRITE(ELCD_CONTROL_REG,POWER_SAVING,32);
// RW_PREPARE_WRITE(ELCD_CONTROL_REG,SOFT_RESET,32);
RW_WRITE(ELCD_CONTROL_REG);
//RW_TEST_READ(ELCD_CONTROL_REG,RESERVED,32);
RW_TEST_READ(ELCD_CONTROL_REG,DMALCD_WU,32);
// RW_TEST_READ(ELCD_CONTROL_REG,ELCD_SECURE,32);
RW_TEST_READ(ELCD_CONTROL_REG,MODE,32);
RW_TEST_READ(ELCD_CONTROL_REG,POWER_SAVING,32);
// RW_TEST_READ(ELCD_CONTROL_REG,SOFT_RESET,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_CONTROL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_ONOFFTIME_REG,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,PRESCALER,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,RON_POLARITY,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,WON_POLARITY,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,WEDGE,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,READ_OFF,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,READ_ON,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,WRITE_OFF,32);
RW_PREPARE_WRITE(ELCD_ONOFFTIME_REG,WRITE_ON,32);
RW_WRITE(ELCD_ONOFFTIME_REG);
RW_TEST_READ(ELCD_ONOFFTIME_REG,PRESCALER,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,RON_POLARITY,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,WON_POLARITY,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,WEDGE,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,READ_OFF,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,READ_ON,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,WRITE_OFF,32);
RW_TEST_READ(ELCD_ONOFFTIME_REG,WRITE_ON,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_ONOFFTIME_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_DMAIT_REG,32);
// RW_PREPARE_WRITE(ELCD_DMAIT_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,RXFIFO_THRESHOLD,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,TXFIFO_THRESHOLD,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,IT_RX_EN,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,IT_TX_EN,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,DMA_RX_EN,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,DMA_TX_EN,32);
RW_PREPARE_WRITE(ELCD_DMAIT_REG,TX_MODE,32);
RW_WRITE(ELCD_DMAIT_REG);
// RW_TEST_READ(ELCD_DMAIT_REG,RESERVED,32);
RW_TEST_READ(ELCD_DMAIT_REG,RXFIFO_THRESHOLD,32);
RW_TEST_READ(ELCD_DMAIT_REG,TXFIFO_THRESHOLD,32);
RW_TEST_READ(ELCD_DMAIT_REG,IT_RX_EN,32);
RW_TEST_READ(ELCD_DMAIT_REG,IT_TX_EN,32);
RW_TEST_READ(ELCD_DMAIT_REG,DMA_RX_EN,32);
RW_TEST_READ(ELCD_DMAIT_REG,DMA_TX_EN,32);
RW_TEST_READ(ELCD_DMAIT_REG,TX_MODE,32);
RW_WRITE_PREVIOUS_VALUE(ELCD_DMAIT_REG);
END_RW_TEST();
BEGIN_RW_TEST(ELCD_TE_REG,32);
// RW_PREPARE_WRITE(ELCD_TE_REG,RESERVED,32);
RW_PREPARE_WRITE(ELCD_TE_REG,VS_COUNTER,32);
RW_PREPARE_WRITE(ELCD_TE_REG,TE_INVERTED,32);
RW_PREPARE_WRITE(ELCD_TE_REG,MODE,32);
RW_PREPARE_WRITE(ELCD_TE_REG,HS_MATCH,32);
RW_PREPARE_WRITE(ELCD_TE_REG,VS_DETECT,32);
RW_PREPARE_WRITE(ELCD_TE_REG,PULSE_DETECT,32);
RW_WRITE(ELCD_TE_REG);
// RW_TEST_READ(ELCD_TE_REG,RESERVED,32);
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