mif.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_PGWST_WELEN_BITPOS);
}


/*
----------------------------------------------------------------------------------
            MIF_SetReadMode                                                      -
----------------------------------------------------------------------------------
*/
void MIF_SetReadMode(MIF_Slow_CS_Enum_t SlowChipSelect,
                     ReadMode_t         input)
{
  /* extract all the fields but ptv field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_RDMODE_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_RDMODE_BITPOS);
}


/*
---------------------------------------------------------------------------
            MIF_SetBusMemoryWidth                                         -
---------------------------------------------------------------------------
*/
void MIF_SetBusMemoryWidth(MIF_Slow_CS_Enum_t SlowChipSelect,
                           BusMemoryWidth_t   input)
{
  /* extract all the fields but ptv field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_BW_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_BW_BITPOS);
}

/*
---------------------------------------------------------------------------
            MIF_GetBusMemoryWidth                                         -
---------------------------------------------------------------------------
*/
BusMemoryWidth_t  MIF_GetBusMemoryWidth(MIF_Slow_CS_Enum_t SlowChipSelect)
{

  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & MIF_BW_MSK;

  BusMemoryWidth_t bw_output = (BusMemoryWidth_t)(value >> MIF_BW_BITPOS);

  return(bw_output);
}



//------------------------------------------------------------------
//            MIF_InitFastInterfaceSDRAMConfigReg                  -
//------------------------------------------------------------------
void MIF_InitFastInterfaceSdramConfigReg
             (MIF_SelfRefreshToggle_t SelfRefreshToggle,
              MIF_ReTiming_t          ReTiming,
              MIF_AutoRefreshMode_t   AutoRefreshMode,
              UWORD8                  SdramType,
              UWORD16                 AutoRefreshCounter,
              MIF_Sdram_Frequency_t   Sdram_Frequency,
              MIF_PowerDownToggle_t   PowerDownToggle,
              MIF_ClockToggle_t       ClockToggle)
{
UWORD32 value;

  /* extract all the fields but Self Refresh Toggle */
  value =   REG32(MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP)
          & ~MIF_SELF_REFRESH_ENABLE_MSK;
  /* add field contents into register */
  value |= SelfRefreshToggle;

  /* Set Re-Timing value */
  value &= ~MIF_RETIMING_MSK;
  value |= (ReTiming << MIF_RETIMING_BITPOS);

  /* Set  Auto Refresh Mode */
  value &= ~MIF_AUTO_REFRESH_MODE_MSK;
  value |= (AutoRefreshMode << MIF_AUTO_REFRESH_MODE_BITPOS);

  /* Set Sdram Type */
  value &= ~MIF_SDRAM_TYPE_MSK;
  value |= (SdramType << MIF_SDRAM_TYPE_BITPOS);

  /* Set auto_refresh_counter field */
  value &= ~MIF_AUTO_REFRESH_COUNTER_MSK;
  value |= (AutoRefreshCounter << MIF_AUTO_REFRESH_COUNTER_BITPOS);

  /* Set Sdram_Frequency  field */
  value &= ~MIF_SDRAM_FREQUENCY_MSK;
  value |= (Sdram_Frequency << MIF_SDRAM_FREQUENCY_BITPOS);

  /* Set PowerDownToggle field */
  value &= ~MIF_POWER_DOWN_ENABLE_MSK;
  value |= (PowerDownToggle << MIF_POWER_DOWN_ENABLE_BITPOS);

  /* Set ClockToggle field */
  value &= ~MIF_CLOCK_SDRAM_DISABLEMSK;
  /* add field contents into register */
  value |= (ClockToggle << MIF_CLOCK_SDRAM_DISABLEBITPOS);

  /* Commit the Register Update */
  REG32(MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP) = value;
}

//------------------------------------------------------------------
//            MIF_CheckFastInterfaceSdramConfigReg
// check if Fast Interface Sdram Config Register is agree with expected values
//------------------------------------------------------------------
BOOL MIF_CheckFastInterfaceSdramConfigReg
             (MIF_SelfRefreshToggle_t SelfRefreshToggle,
              MIF_ReTiming_t          ReTiming,
              MIF_AutoRefreshMode_t   AutoRefreshMode,
              UWORD8                  SdramType,
              UWORD16              	  AutoRefreshCounter,
              MIF_Sdram_Frequency_t   Sdram_Frequency,
              MIF_PowerDownToggle_t   PowerDownToggle,
              MIF_ClockToggle_t       ClockToggle)
{
UWORD32 value;
BOOL ok = True;

  value = REG32(MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP);

  if ((value & MIF_SELF_REFRESH_ENABLE_MSK) != SelfRefreshToggle)
  		ok=False;


  if ((value & MIF_RETIMING_MSK) != (ReTiming << MIF_RETIMING_BITPOS))
  		ok=False;

  /* Set  Auto Refresh Mode */
  if ((value & MIF_AUTO_REFRESH_MODE_MSK) != (AutoRefreshMode << MIF_AUTO_REFRESH_MODE_BITPOS))
  		ok=False;

  /* Set Sdram Type */
  if ((value & MIF_SDRAM_TYPE_MSK) != (SdramType << MIF_SDRAM_TYPE_BITPOS))
  		ok=False;

  /* Set auto_refresh_counter field */
  if ((value & MIF_AUTO_REFRESH_COUNTER_MSK) !=(AutoRefreshCounter << MIF_AUTO_REFRESH_COUNTER_BITPOS))
  		ok=False;

  /* Set Sdram_Frequency  field */
  if ((value & MIF_SDRAM_FREQUENCY_MSK) !=(Sdram_Frequency << MIF_SDRAM_FREQUENCY_BITPOS))
  		ok=False;

  /* Set PowerDownToggle field */
  if ((value & MIF_POWER_DOWN_ENABLE_MSK) != (PowerDownToggle << MIF_POWER_DOWN_ENABLE_BITPOS))
  		ok=False;

  /* Set ClockToggle field */
  if ((value & MIF_CLOCK_SDRAM_DISABLEMSK) !=(ClockToggle << MIF_CLOCK_SDRAM_DISABLEBITPOS))
  		ok=False;

return(ok);
}

//--------------------------------------------------------------------------
// MIF_GetFastInterfaceSdramConfigReg
//--------------------------------------------------------------------------
UWORD32  MIF_GetFastInterfaceSdramConfigReg(void)
{
return(REG32(MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP));
}

//--------------------------------------------------------------------------
//            MIF_InitFastInterfaceSdramMrsReg                             -
//--------------------------------------------------------------------------
void MIF_InitFastInterfaceSdramMrsReg(MIF_CasLatency_t CasLatency)
{
UWORD32 value ;
  value = REG32(MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP);
  value &= ~MIF_CAS_LATENCY_MSK;
  /* add field contents into register */
  value |= (CasLatency  << MIF_CAS_LATENCY_BITPOS);
  /* Commit the Register Update */
  REG32(MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP) = value;
}

//--------------------------------------------------------------------------
// MIF_GetFastInterfaceSdramMrsReg
//--------------------------------------------------------------------------
UWORD32  MIF_GetFastInterfaceSdramMrsReg(void)
{
return(REG32(MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP));
}

//---------------------------------------------------------------------
// NAME        : MIF_MifSetPowerDown
//
// DESCRIPTION : Switch on or off the internal EMIF clock
//
// SYNOPSYS    : void MIF_MifSetPowerDown(BOOL State)
//
// PARAMETERS  : State               SWITCH_ON or SWITCH_OFF
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
void MIF_SetPowerDown(BOOL State)
{
  if (State==SWITCH_OFF)
    {
    ClearBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PDE_MASK);
    }
  else
    {
    SetBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PDE_MASK);
    }
}

//---------------------------------------------------------------------
// NAME        : MIF_MifSetPowerDown
//
// DESCRIPTION : Switch on or off the internal EMIF clock
//
// SYNOPSYS    : void MIF_MifSetPowerDown(BOOL GlobalPde, BOOL ImifPde)
//
// PARAMETERS  : GlobalPde               POWER_DOWN or NOT_POWER_DOWN
//
//               ImifPde                           idem
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
void MIF_MifSetPowerDown(BOOL GlobalPde, BOOL ImifPde)
{
  if (GlobalPde==POWER_DOWN)
    {
    SetBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PDE_MASK);
    }
  else
    {
    ClearBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PDE_MASK);
    }

  if (ImifPde==POWER_DOWN)
    {
    SetBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PWD_EN_MASK);
    }
  else
    {
    ClearBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PWD_EN_MASK);
    }
}

//---------------------------------------------------------------------
// NAME        : MIF_MifGetPowerDown
//
// DESCRIPTION : get back the state of power down mode Switch on or off
//
// SYNOPSYS    : BOOL MIF_MifSetPowerDown(void)
//
// PARAMETERS  : None
//
// RETURN VALUE: State               SWITCH_ON or SWITCH_OFF
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL MIF_MifGetPowerDown(void)
{
  if (TestBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_PDE_MASK))
    {
    return((BOOL)SWITCH_ON);
    }
  else
    {
    return((BOOL)SWITCH_OFF);
    }
}

//---------------------------------------------------------------------
// NAME        : MIF_MifSetWriteProtect
//
// DESCRIPTION : Set the write protect mode
//
// SYNOPSYS    : void MIF_MifSetWriteProtect(BOOL State)
//
// PARAMETERS  : State              WRITE_FORBIDEN or WRITE_AUTHORIZED
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
void MIF_MifSetWriteProtect(BOOL State)
{
  if (State==WRITE_AUTHORIZED)
    {
    SetBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_WP_MASK);
    }
  else
    {
    ClearBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_WP_MASK);
    }
}

//---------------------------------------------------------------------
// NAME        : MIF_MifGetWriteProtect
//
// DESCRIPTION : Get the write protect mode
//
// SYNOPSYS    : BOOL MIF_MifGetWriteProtect(void)
//
// PARAMETERS  : None
//
// RETURN VALUE: WRITE_FORBIDEN or WRITE_AUTHORIZED
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL MIF_MifGetWriteProtect(void)
{
  if (TestBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_WP_MASK))
    {
    return((BOOL)WRITE_FORBIDEN);
    }
  else
    {
    return((BOOL)WRITE_AUTHORIZED);
    }
}

//---------------------------------------------------------------------
// NAME        : MIF_MifTestBootMode
//
// DESCRIPTION : Test if the flash is on CS0 or CS3
//
// SYNOPSYS    : BOOL MIF_MifTestBootMode(void)
//
// PARAMETERS  : None
//
// RETURN VALUE: FLASH_ON_CS0 or FLASH_ON_CS3
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL MIF_MifTestBootMode(void)
{
   if (TestBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_BM_MASK))
       {
       return((BOOL)FLASH_ON_CS3);
       }
   else
       {
       return((BOOL)FLASH_ON_CS0);
       }

}

//---------------------------------------------------------------------
// NAME        : MIF_MifSetBootMode
//
// DESCRIPTION : Test if the flash is on CS0 or CS3
//
// SYNOPSYS    : void MIF_MifSetBootMode(BOOL)
//
// PARAMETERS  : FLASH_ON_CS0 or FLASH_ON_CS3
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
void MIF_MifSetBootMode(BOOL State)
{
   if (State==FLASH_ON_CS3)
     {
     SetBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_BM_MASK);
     }
   else
     {
     ClearBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_BM_MASK);
     }

}

//---------------------------------------------------------------------
// NAME        : MIF_MifTestFlashReady
//
// DESCRIPTION : Test if the flash package is ready
//
// SYNOPSYS    : BOOL MIF_MifTestFlashReady(void)
//
// PARAMETERS  : None
//
// RETURN VALUE: FLASH_READY or FLASH_NOT_READY
//
// LIMITATIONS : None
//
//
//
//---------------------------------------------------------------------
BOOL MIF_MifTestFlashReady(void)
{
   if (TestBit(REG32(MIF_CONFIG_REG_ADDR_SUP),MIF_CONFREG_RDY_MASK))
       {
       return((BOOL)FLASH_READY);
       }
   else
       {
       return((BOOL)FLASH_NOT_READY);
       }

}

//---------------------------------------------------------------------
// NAME        : MIF_EnableDSPEndianismTranslation
//
// DESCRIPTION : Switch on or off DSP endianism translation
//
// SYNOPSYS    : void MIF_EnableDSPEndianismTranslation(BOOL)
//
// PARAMETERS  : State               SWITCH_ON or SWITCH_OFF
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
void MIF_EnableDSPEndianismTranslation(BOOL State)
{
  if (State==SWITCH_OFF)
    {
    ClearBit(REG32(MIF_ENDIANISM_CONFIG_REG_ADDR),MIF_ENDIANISM_EN_MASK);
    }
  else
    {
    SetBit(REG32(MIF_ENDIANISM_CONFIG_REG_ADDR),MIF_ENDIANISM_EN_MASK);
    }
}

//-----------------------------------------------------------------------------
// NAME        : MIF_EnableDSPByteSwap
// DESCRIPTION : Switch on or off DSP endianism translation Byte swap or Word swap
// PARAMETERS  : State               SWITCH_ON or SWITCH_OFF
// RETURN VALUE: None.
// LIMITATIONS : None.
//-----------------------------------------------------------------------------
 void MIF_EnableDSPByteSwap(BOOL State)
{
  if (State==SWITCH_OFF)
    {
    ClearBit(REG32(MIF_ENDIANISM_CONFIG_REG_ADDR),MIF_ENDIANISM_BS_EN_MASK);
    }
  else
    {
    SetBit(REG32(MIF_ENDIANISM_CONFIG_REG_ADDR),MIF_ENDIANISM_BS_EN_MASK);
    }
}