mif.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION

   Property of Texas Instruments
   For  Unrestricted  Internal  Use  Only
   Unauthorized reproduction and/or distribution is strictly prohibited.
   This product is protected under copyright law and trade secret law
   as an unpublished work.
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
   Filename       	: MIF.c

   Description    	: Header file for the memory interface module

   Project        	: Satustar

   Author         	: Francois Reygagne

===============================================================================
*/

#include "mif.h"
#include "mem.h"
#include "result.h"


/* Table giving the Chip Selects Register Address to test */
static const REgAddrSlowCS_t  REgAddrSlowCSSup
  = { MIF_nCS0_CONFIG_REG_ADDR_SUP , MIF_nCS1_CONFIG_REG_ADDR_SUP ,
      MIF_nCS2_CONFIG_REG_ADDR_SUP , MIF_nCS3_CONFIG_REG_ADDR_SUP };

static const REgAddrSlowCS_t  REgAddrSlowCSUser
  = { MIF_nCS0_CONFIG_REG_ADDR_USR , MIF_nCS1_CONFIG_REG_ADDR_USR ,
      MIF_nCS2_CONFIG_REG_ADDR_USR , MIF_nCS3_CONFIG_REG_ADDR_USR };

//---------------------------------------------------------------------
// NAME        : MIF_CheckResetEmifPriority
//
// DESCRIPTION : Verify the reset value
//
// SYNOPSYS    : BOOL MIF_CheckResetEmifPriority(const MIF_ExternalBusId_t BusId)
//
// PARAMETERS  : BusId                           MIF_EXTERNAL_SLOW_BUS
//                                               MIF_EXTERNAL_FAST_BUS
//
// RETURN VALUE: IS_OK or NOT_OK
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL MIF_CheckResetEmifPriority(const MIF_ExternalBusId_t BusId)
{
UWORD32 PriorityRegAddr;
BOOL    Status;

  if ( BusId == MIF_EXTERNAL_SLOW_BUS )
     PriorityRegAddr = MIF_PRIORITY_EMIF_REG0_ADDR_USR;
  else
     /* This is an external Fast bus */
     PriorityRegAddr = MIF_PRIORITY_EMIF_REG1_ADDR_USR;

  if ( *(UWORD32*)PriorityRegAddr == MIF_PRIORITY_EMIF_RESET_VALUE )
       Status=(BOOL)IS_OK;
  else Status=(BOOL)NOT_OK;

  return Status;
}


/*
-----------------------------------------------------------------------------
    MIF_CheckResetIMIFPriority                                              -
-----------------------------------------------------------------------------
*/
int MIF_CheckResetImifPriority(void)
{
UWORD8 Status;
  if ( *(UWORD32*)MIF_PRIORITY_IMIF_REG_ADDR_USR == MIF_PRIORITY_IMIF_RESET_VALUE )
       Status=RES_OK;
  else Status=RES_BAD;

 RES_Set(Status);

return Status;
}


/*
-----------------------------------------------------------------------------
    MIF_CheckResetMifConfigReg                                              -
-----------------------------------------------------------------------------
*/
int MIF_CheckResetMifConfigReg(void)
{
UWORD8 Status;
UWORD32 value;
 value = ((*(UWORD32*)MIF_CONFIG_REG_ADDR_USR) & 0xD); // keep only bits 0, 2 & 3

 if ( value == MIF_CONFIG_REG_RESET_VALUE )
       Status=RES_OK;
  else Status=RES_BAD;

 RES_Set(Status);

return Status;
}

//---------------------------------------------------------------------
// NAME        : MIF_CheckResetSlowCSConfigReg
//
// DESCRIPTION : Test the value at reset of
//
// SYNOPSYS    : BOOL MIF_CheckResetSlowCSConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect)
//
// PARAMETERS  : SlowChipSelect             MIF_Slow_nCS0
//                                          MIF_Slow_nCS1
//                                          MIF_Slow_nCS2
//                                          MIF_Slow_nCS3
//
// RETURN VALUE: IS_OK or NOT_OK
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL MIF_CheckResetSlowCSConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect)
{
BOOL Status;
  if ( *(UWORD32*)REgAddrSlowCSUser[SlowChipSelect] == MIF_SLOW_CS_CONFIG_REG_RESET_VALUE )

       Status=(BOOL)IS_OK;
  else Status=(BOOL)NOT_OK;


return Status;
}

//---------------------------------------------------------------------
// NAME        : MIF_MifGetConfigReg
//
// DESCRIPTION : Get the value of the register
//
// SYNOPSYS    : UWORD32 MIF_MifGetConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect)
//
// PARAMETERS  : SlowChipSelect             MIF_Slow_nCS0
//                                          MIF_Slow_nCS1
//                                          MIF_Slow_nCS2
//                                          MIF_Slow_nCS3
//
// RETURN VALUE: value of the register
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
UWORD32 MIF_MifGetConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect)
{


return (REG32(REgAddrSlowCSUser[SlowChipSelect]));
}


/*
------------------------------------------------------------------------
   MIF_CheckResetFastInterfaceSdramConfigReg                           -
------------------------------------------------------------------------
*/
int MIF_CheckResetFastInterfaceSdramConfigReg(void)
{
UWORD8 Status;
  if ( *(UWORD32*)MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_USR == MIF_FAST_IF_SDRAM_CONFIG_REG_RESET_VALUE )
       Status=RES_OK;
  else Status=RES_BAD;

 RES_Set(Status);

return Status;
}

/*
------------------------------------------------------------------------
   MIF_CheckResetFastInterfaceSdramMrsReg                              -
------------------------------------------------------------------------
*/
int MIF_CheckResetFastInterfaceSdramMrsReg(void)
{
UWORD8 Status;
  if ( *(UWORD32*)MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_USR == MIF_FAST_IF_SDRAM_MRS_REG_RESET_VALUE )
       Status=RES_OK;
  else Status=RES_BAD;

 RES_Set(Status);

return Status;
}


/*
-----------------------------------------------------------------------------
             MIF_SetEmifPriority                                            -
-----------------------------------------------------------------------------
*/
void MIF_SetEmifPriority(const MIF_ExternalBusId_t BusId,
                         const UWORD8 HostConsecutiveAccess,
                         const UWORD8 DmaConsecutiveAccess,
                         const UWORD8 DspConsecutiveAccess,
                         const UWORD8 ArmConsecutiveAccess)
{
UWORD32 PriorityRegAddr;
UWORD32 value;

  if ( BusId == MIF_EXTERNAL_SLOW_BUS )
     PriorityRegAddr = MIF_PRIORITY_EMIF_REG0_ADDR_SUP;
  else
     /* This is an external Fast bus */
     PriorityRegAddr = MIF_PRIORITY_EMIF_REG1_ADDR_SUP;

  /* extract all the fields but Arm consecutive access */
  value = *(UWORD32*)PriorityRegAddr & ~MIF_ARM_PRIORITY_MSK;
  /* add field contents into register */
  value |= ArmConsecutiveAccess;

  value &= ~MIF_DSP_PRIORITY_MSK;
  value |= (DspConsecutiveAccess << MIF_DSP_PRIORITY_BITPOS);

  value &= ~MIF_DMA_PRIORITY_MSK;
  value |= (DmaConsecutiveAccess << MIF_DMA_PRIORITY_BITPOS);

  value &= ~MIF_HOST_PRIORITY_MSK;
  value |= (HostConsecutiveAccess << MIF_HOST_PRIORITY_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)PriorityRegAddr = value;
}

/*
-----------------------------------------------------------------------------
             MIF_SetImifPriority                                            -
-----------------------------------------------------------------------------
*/
void MIF_SetImifPriority(const UWORD8 ArmConsecutiveAccess,
                         const UWORD8 DspConsecutiveAccess,
                         const UWORD8 DmaConsecutiveAccess,
                         const UWORD8 HostConsecutiveAccess)
{
UWORD32 value;

  /* extract all the fields but Arm consecutive access */
  value = *(UWORD32*)MIF_PRIORITY_IMIF_REG_ADDR_SUP & ~MIF_ARM_PRIORITY_MSK;
  /* add field contents into register */
  value |= ArmConsecutiveAccess;

  value &= ~MIF_DSP_PRIORITY_MSK;
  value |= (DspConsecutiveAccess << MIF_DSP_PRIORITY_BITPOS);

  value &= ~MIF_DMA_PRIORITY_MSK;
  value |= (DmaConsecutiveAccess << MIF_DMA_PRIORITY_BITPOS);

  value &= ~MIF_HOST_PRIORITY_MSK;
  value |= (HostConsecutiveAccess << MIF_HOST_PRIORITY_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)MIF_PRIORITY_IMIF_REG_ADDR_SUP = value;

}

//---------------------------------------------------------------------
// NAME        : MIFTST_EmifInitSlowCSConfigReg
//
// DESCRIPTION : Initialize the SlowCS Config register
//
// SYNOPSYS    : void MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect,
//                             BusMemoryWidth_t   bus_memory_width,
//                             ReadMode_t         read_mode,
//                             UWORD8             pgwst_welen,
//                             UWORD8             write_wait_state,
//                             UWORD8             read_wait_state,
//                             PnF_t              pipeline_flowthrough,
//                             boolean_t          retimed_disable,
//                             FCLKDIV_t          flash_clock_divider,
//                             )
//
//
//
// PARAMETERS  :
//
//                  SlowChipSelect             MIF_Slow_nCS0
//                                             MIF_Slow_nCS1
//                                             MIF_Slow_nCS2
//                                             MIF_Slow_nCS3
//
//                  bus_memory_width           MIF_MEMORY_16BIT_WIDE or MIF_MEMORY_32BIT_WIDE
//
//                  read_mode                  MIF_ASYNC_READ
//                                             MIF_PAGE_ROM_READ_WORDS4
//                                             MIF_PAGE_ROM_READ_WORDS8
//                                             MIF_PAGE_ROM_READ_WORDS16
//                                             MIF_SYNC_BURST_READ_TI
//                                             MIF_SYNC_BURST_READ_SMART3
//                                             MIF_SYNC_READ_WRITE_ZBT
//
//                  pgwst_welen                WE length (0-15)
//
//                  write_wait_state           Number of write wait state (0-15)
//
//                  read_wait_state            Number of read wait state (0-5)
//
//                  pipeline_flowthrough       FLOW_THROUGH or PIPELINE_MODE
//
//                  retimed_disable            ENABLE or DISABLE
//
//                  flash_clock_divider        MIF_DIVIDE_BY_1
//                                             MIF_DIVIDE_BY_2
//                                             MIF_DIVIDE_BY_4
//                                             MIF_DIVIDE_BY_6
//
//                  Package_t                  FLASH_INTEL or NO_FLASH_INTEL
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//
//
//
//---------------------------------------------------------------------
void MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_CS_Enum_t SlowChipSelect,
                             BusMemoryWidth_t   bus_memory_width,
                             ReadMode_t         read_mode,
                             UWORD8             pgwst_welen,
                             UWORD8             write_wait_state,
                             UWORD8             read_wait_state,
                             PnF_t              pipeline_flowthrough,
                             RetimingControl_t  retimed_disable,
                             FCLKDIV_t          flash_clock_divider,
                             Package_t          IsItFlashIntel
                             )
{
UWORD32 value;

  /* extract all the fields but clock divisor */
  value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_FCLKDIV_MSK;
  /* add field contents into register */
  value |= flash_clock_divider;

 /* extract all the fields but retimed_switch */
  value &= ~MIF_RT_MSK;
  /* add field contents into register */
  value |= (retimed_disable << MIF_RT_BITPOS);

  /* extract all the fields but retimed_switch */
  value &= ~MIF_PNF_MSK;
  /* add field contents into register */
  value |= (pipeline_flowthrough << MIF_PNF_BITPOS);

  /* extract all the fields but Read_Wait States field */
  value &= ~MIF_RDWST_MSK;
  /* add field contents into register */
  value |= (read_wait_state << MIF_RDWST_BITPOS);

  /* extract all the fields but write_wait states field */
  value &= ~MIF_WRWST_MSK;
  /* add field contents into register */
  value |= (write_wait_state << MIF_WRWST_BITPOS);

  /* extract all the fields but welen field */
  value &= ~MIF_PGWST_WELEN_MSK;
  /* add field contents into register */
  value |= (pgwst_welen << MIF_PGWST_WELEN_BITPOS);

  /* extract all the fields but ptv field */
  value &= ~MIF_RDMODE_MSK;
  /* add field contents into register */
  value |= (read_mode << MIF_RDMODE_BITPOS);

  /* extract all the fields but ptv field */
  value &= ~MIF_BW_MSK;
  /* add field contents into register */
  value |= (bus_memory_width << MIF_BW_BITPOS);

  /* extract all the fields but ptv field */
  value &= ~MIF_FINTEL_MSK;
  /* add field contents into register */
  value |= (IsItFlashIntel << MIF_FINTEL_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value;
}


/*
-------------------------------------------------------------------------
            MIF_SetFlashClockDivider                                    -
-------------------------------------------------------------------------
*/
void MIF_SetFlashClockDivider(MIF_Slow_CS_Enum_t SlowChipSelect,
                              FCLKDIV_t          input)
{
UWORD32 value;
  /* extract all the fields but ptv field */
  value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_FCLKDIV_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | input;
}


/*
----------------------------------------------------------------------------
            MIF_SetRetimedSwitch                                           -
----------------------------------------------------------------------------
*/
void MIF_SetRetimedSwitch(MIF_Slow_CS_Enum_t SlowChipSelect,
                          RetimingControl_t  input)
{
  /* extract all the fields but Retiming Control field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_RT_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_RT_BITPOS);
}


/*
--------------------------------------------------------------------------------
            MIF_SetReadWaitState                                               -
--------------------------------------------------------------------------------
*/
void MIF_SetReadWaitState(MIF_Slow_CS_Enum_t SlowChipSelect,
                          UWORD8               input)
{
  /* extract all the fields but ptv field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_RDWST_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_RDWST_BITPOS);
}


/*
-----------------------------------------------------------------------------
            MIF_SetWriteWaitState                                           -
-----------------------------------------------------------------------------
*/
void MIF_SetWriteWaitState(MIF_Slow_CS_Enum_t SlowChipSelect,
                           UWORD8               input)
{
  /* extract all the fields but ptv field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_WRWST_MSK;
  /* add field contents into register */
  *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] = value | (input << MIF_WRWST_BITPOS);
}


/*
----------------------------------------------------------------------------------
            MIF_SetPgwstWelen                                                    -
----------------------------------------------------------------------------------
*/
void MIF_SetPgwstWelen(MIF_Slow_CS_Enum_t SlowChipSelect,
                       UWORD8               input)
{
  /* extract all the fields but ptv field */
  UWORD32 value = *(UWORD32*)REgAddrSlowCSSup[SlowChipSelect] & ~MIF_PGWST_WELEN_MSK;