📄 rheatest.c
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RHEA_SetHighFrequency();
return(result);
}
UWORD16 RHEATST_CheckAbortRheaMisMatch(RHEA_Request_t IsRequestType,
RHEA_Access_Size_t IsMemoryAccessSize,
RHEA_Access_Size_t IsPeripheralAccessSize,
UWORD32 IsFaultAddress,
UWORD32 IsData)
{
boolean_t TimeOut;
boolean_t AccessSizeMismatch;
RHEA_Request_t Request;
boolean_t NotSupervisorMode;
RHEA_Access_Size_t MemoryAccessSize;
RHEA_Access_Size_t PeriphAccessSize;
UWORD16 FaultAddress;
UWORD16 error;
error=0;
RHEA_ReadDebugCtrolSignal(&TimeOut, &AccessSizeMismatch,
&Request, &NotSupervisorMode,
&MemoryAccessSize, &PeriphAccessSize);
if ((!TimeOut) && (AccessSizeMismatch))
{
if (MemoryAccessSize == IsMemoryAccessSize)
{
FaultAddress = RHEA_ReadFaultAddress();
if ((IsFaultAddress & RHEA_ADDR_MASK) != FaultAddress)
error = 3 ;
if (Request != IsRequestType)
error = 4 ;
if (MemoryAccessSize != IsMemoryAccessSize)
error = 5 ;
if (PeriphAccessSize != IsPeripheralAccessSize)
error = 6 ;
/*
if (IsRequestType==RHEA_WRITE_REQUEST)
{
if (IsMemoryAccessSize == RHEA_BITS32_SIZE)
FaultData = (RHEA_ReadFaultDataHigh() << 16 | RHEA_ReadFaultDataLow());
if (IsMemoryAccessSize == RHEA_BITS16_SIZE)
FaultData = RHEA_ReadFaultDataLow();
if (IsMemoryAccessSize == RHEA_BITS8_SIZE)
FaultData = RHEA_ReadFaultDataLow() & 0xFF;
if (FaultData != IsData)
ok=False;
}
*/
}
else
{
error =2 ;
}
}
else
{
error = 1 ;
}
return(error);
}
UWORD16 RHEATST_CheckAbortRheaTimeOut(RHEA_Request_t IsRequestType,
RHEA_Access_Size_t IsMemoryAccessSize,
UWORD32 IsFaultAddress,
UWORD32 IsData)
{
boolean_t TimeOut;
boolean_t AccessSizeMismatch;
RHEA_Request_t Request;
boolean_t NotSupervisorMode;
RHEA_Access_Size_t MemoryAccessSize;
RHEA_Access_Size_t PeriphAccessSize;
UWORD16 FaultAddress;
UWORD16 error;
error=0;
RHEA_ReadDebugCtrolSignal(&TimeOut, &AccessSizeMismatch,
&Request, &NotSupervisorMode,
&MemoryAccessSize, &PeriphAccessSize);
if ((TimeOut) && (!AccessSizeMismatch))
{
if (MemoryAccessSize == IsMemoryAccessSize)
{
FaultAddress = RHEA_ReadFaultAddress();
if ((IsFaultAddress & RHEA_ADDR_MASK) != FaultAddress)
error =12 ;
if (Request != IsRequestType)
error =13 ;
if (MemoryAccessSize != IsMemoryAccessSize)
error =14 ;
/*
if (IsRequestType==RHEA_WRITE_REQUEST)
{
if (IsMemoryAccessSize == RHEA_BITS32_SIZE)
FaultData = (RHEA_ReadFaultDataHigh() << 16 | RHEA_ReadFaultDataLow());
if (IsMemoryAccessSize == RHEA_BITS16_SIZE)
FaultData = RHEA_ReadFaultDataLow();
if (IsMemoryAccessSize == RHEA_BITS8_SIZE)
FaultData = RHEA_ReadFaultDataLow() & 0xFF;
if (FaultData != IsData)
ok=False;
}
*/
}
else
{
error =11 ;
}
}
else
{
error = 10 ;
}
return(error);
}
//-------------------------------------------------------------------
// RHEATEST_TimeOut
//-------------------------------------------------------------------
void RHEATST_Timeout (UWORD32 Strobe0Address,
UWORD32 Strobe1Address,
volatile UWORD8 * const CounterIrqRhea)
{
UWORD16 error;
UWORD32 i;
// init rhea bridge
RHEA_InitEnhancedRheaCtrolReg(RHEA_TIMEOUT_ENABLE,
RHEA_INTERRUPT_ENABLE,
RHEA_HIGH_FREQUENCY_ENABLE,
RHEA_DISABLE_ABORT);
//time_out= 10 provoque une erreur
RHEA_InitCtrolReg(RHEA_FACTOR2_STROBE,RHEA_FACTOR2_STROBE, TIMEOUT_RHEA);
// disable write buffer on strobe 0, disable on strobe 1
RHEA_SetPostedWrite(RHEA_DISABLE_WRITE_BUFFER_STROBE0,
RHEA_DISABLE_WRITE_BUFFER_STROBE1);
// WARNING:
// ABORT on WRITE ACCESS can't be checked
// Because we'll catch an Abort which route
// to the EX_AbortD procedure implemented in the main test program
// but we can't go back to the origin of error
*CounterIrqRhea=0;
// Write a value on a missing peripheral on strobe 0
*(UWORD16*)Strobe0Address = 0x1234;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;};
if (i==MAX_WAIT_IT_RHEA)
RES_Set(0xBAD);
else
{
error=RHEATST_CheckAbortRheaTimeOut(RHEA_WRITE_REQUEST,
RHEA_BITS16_SIZE,
Strobe0Address,
0x1234);
if (error)
RES_Set(error);
else
RES_Set(RES_OK);
}
*CounterIrqRhea=0;
// wait interrupt event
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
RES_Set(0xBAD);
else
{
error=RHEATST_CheckAbortRheaTimeOut(RHEA_READ_REQUEST,RHEA_BITS16_SIZE,
Strobe0Address,0);
if (error)
RES_Set(error);
else
RES_Set(RES_OK);
}
*CounterIrqRhea=0;
// Write a value on a missing peripheral on strobe 1
*(UWORD16*)Strobe1Address = 0x1234;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
RES_Set(0xBAD);
else
{
error=RHEATST_CheckAbortRheaTimeOut(RHEA_WRITE_REQUEST,
RHEA_BITS16_SIZE,
Strobe1Address,0x1234);
if (error)
RES_Set(error);
else
RES_Set(RES_OK);
}
*CounterIrqRhea=0;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
RES_Set(0xBAD);
else
{
error=RHEATST_CheckAbortRheaTimeOut(RHEA_READ_REQUEST,
RHEA_BITS16_SIZE,
Strobe1Address,0);
if (error)
RES_Set(error);
else
RES_Set(RES_OK);
}
}
//-------------------------------------------------------------------
// RHEATST_AccessSizeMismatch
//-------------------------------------------------------------------
UWORD16 RHEATST_AccessSizeMismatch (volatile UWORD8 * const CounterIrqRhea)
{
#define VALUE32 0x0FACD5A5a
#define VALUE16 0x0AA55
#define VALUE8 0x0A5
UWORD32 i;
UWORD8 * ptr_uword8;
BOOL ok = True;
volatile UWORD32 tmp32;
volatile UWORD16 tmp16;
volatile UWORD8 tmp8;
// enable timeout access and Irq generation instead of abort generation
RHEA_InitEnhancedRheaCtrolReg(RHEA_TIMEOUT_ENABLE,
RHEA_INTERRUPT_ENABLE,
RHEA_HIGH_FREQUENCY_ENABLE,
RHEA_DISABLE_ABORT);
/* Set access factors and timeout */
RHEA_InitCtrolReg(RHEA_FACTOR2_STROBE,RHEA_FACTOR2_STROBE, TIMEOUT_RHEA);
/* Disable Write Buffer : Not Posted Write */
RHEA_SetPostedWrite(RHEA_DISABLE_WRITE_BUFFER_STROBE0,
RHEA_DISABLE_WRITE_BUFFER_STROBE1);
/************ ABORT ON WRITE ACCESS CAN'T BE TESTED *******************
*CounterIrqRhea=0;
// --------------------------------------------------------
// write access on 32 bits on Strobe 0 CS10 (8 bits memory)
// --------------------------------------------------------
ptr_uword32 = (UWORD32 *) MEM_RHEA_STROBE0_CS10_ADDR;
*ptr_uword32 = VALUE32;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
ok=False;
if (!RHEATST_CheckAbortRheaMisMatch(RHEA_READ_REQUEST,
RHEA_BITS32_SIZE, // access size
RHEA_BITS8_SIZE , // perif size
MEM_RHEA_STROBE0_CS10_ADDR,VALUE32)) // adress error
ok= False;
*****************************************************************************/
// --------------------------------------------------------
// read access on 8 bits on Strobe 0 CS11 (16 bits memory)
// --------------------------------------------------------
*CounterIrqRhea=0;
// access on read on 8 bits
ptr_uword8 = (UWORD8 *) MEM_RHEA_STROBE0_CS11_ADDR ;
tmp8= *ptr_uword8;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
ok=False;
if (!RHEATST_CheckAbortRheaMisMatch(RHEA_READ_REQUEST,
RHEA_BITS8_SIZE, // access size
RHEA_BITS16_SIZE, // perif size
MEM_RHEA_STROBE0_CS11_ADDR,0)) // adress error
ok= False;
/************ ABORT ON WRITE ACCESS CAN'T BE TESTED *******************
// --------------------------------------------------------
// write access on 16 bits on Strobe 1 CS4 (32 bits memory)
// --------------------------------------------------------
*CounterIrqRhea=0;
ptr_uword16 = (UWORD16 *) MEM_RHEA_STROBE1_CS4_ADDR;
*ptr_uword16 = VALUE16;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
ok=False;
if (!RHEATST_CheckAbortRheaMisMatch(RHEA_WRITE_REQUEST,
RHEA_BITS16_SIZE, // access size
RHEA_BITS32_SIZE , // perif size
MEM_RHEA_STROBE1_CS4_ADDR,VALUE16)) // adress error
ok= False;
**********************************************************************/
/*
// --------------------------------------------------------
// read access on 32 bits on Strobe 1 CS6 (8 bits memory)
// --------------------------------------------------------
*CounterIrqRhea=0;
// write access on 16 bits
ptr_uword32 = (UWORD32 *) MEM_RHEA_STROBE1_CS6_ADDR;
tmp32 = *ptr_uword32 ;
// wait interrupt event
i=0;
while ((*CounterIrqRhea == 0) && (i<MAX_WAIT_IT_RHEA))
{i++;}
if (i==MAX_WAIT_IT_RHEA)
ok=False;
if (!RHEATST_CheckAbortRheaMisMatch(RHEA_WRITE_REQUEST,
RHEA_BITS32_SIZE, // access size
RHEA_BITS8_SIZE , // perif size
MEM_RHEA_STROBE1_CS6_ADDR,0)) // adress error
ok= False;
*/
if (ok)
return RES_OK;
else
return RES_BAD;
}
//-------------------------------------------------------------------
// RHEATST_AbortGeneration
//-------------------------------------------------------------------
UWORD16 RHEATST_AbortGeneration(UWORD32 MissingPeripheralAddress)
{
RHEA_InitEnhancedRheaCtrolReg(RHEA_TIMEOUT_ENABLE,
RHEA_INTERRUPT_DISABLE,
RHEA_HIGH_FREQUENCY_ENABLE,
RHEA_ENABLE_ABORT);
/* Set access factors and timeout */
RHEA_InitCtrolReg(RHEA_FACTOR2_STROBE,RHEA_FACTOR2_STROBE, TIMEOUT_RHEA);
/* Disable Write Buffer : Not Posted Write */
RHEA_SetPostedWrite(RHEA_DISABLE_WRITE_BUFFER_STROBE0,
RHEA_DISABLE_WRITE_BUFFER_STROBE1);
// WARNING:
// The following operations should generate a abort data
// Write a value on a missing peripheral on strobe 0
*(UWORD16*)MissingPeripheralAddress = 0;
// if we execute something after the lastest instruction, it is not OK
return(RES_BAD);
}
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