spiw.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

						
						
//		Filename		:spiw.h		
//						
//		Date		of	Module	Modification:
//		Date		of	Generation	:11/10/05
//						
//						
//========================================================================						

#ifndef		_SPIW__H				
#define		_SPIW__H				
#include	"mapping.h"	
#include 	"global_types.h"		
//BEGIN		INC		GENERATION		
//--------------------------------------						
#define		SPI_REV_OFFSET		0x00		
#define		SPI_SCR_OFFSET		0x10		
#define		SPI_SSR_OFFSET		0x14		
#define		SPI_ISR_OFFSET		0x18		
#define		SPI_IER_OFFSET		0x1C		
#define		SPI_SET1_OFFSET		0x24		
#define		SPI_SET2_OFFSET		0x28		
#define		SPI_CTRL_OFFSET		0x2C		
#define		SPI_DSR_OFFSET		0x30		
#define		SPI_TX_OFFSET		0x34		
#define		SPI_RX_OFFSET		0x38		
#define		SPI_TEST_OFFSET		0x3C		





//SPI_REV						
//-------------------						
#define		SPI_REV						REG32(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET)		

#define		SPI_REV_RESERVED_POS				8		
#define		SPI_REV_RESERVED_NUMB				24		
#define		SPI_REV_RESERVED_RES_VAL			0x000000		
//R						

#define		SPI_REV_REV_POS						0		
#define		SPI_REV_REV_NUMB					8		
#define		SPI_REV_REV_RES_VAL					0x20		
//R						

//SPI_SCR						
//-------------------						
#define		SPI_SCR_REG					REG32(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET)		
#define		SPI_SCR_RESERVED_0_POS				5		
#define		SPI_SCR_RESERVED_0_NUMB				27		
#define		SPI_SCR_RESERVED_0_RES_VAL			0x0000000		
//R						

#define		SPI_SCR_IDLEMODE_POS				3		
#define		SPI_SCR_IDLEMODE_NUMB				2		
#define		SPI_SCR_IDLEMODE_RES_VAL			0x0		
//R/W						

#define		SPI_SCR_ENAWAKEUP_POS				2		
#define		SPI_SCR_ENAWAKEUP_NUMB				1		
#define		SPI_SCR_ENAWAKEUP_RES_VAL			0x0		
//R/W						

#define		SPI_SCR_SOFTRESET_POS				1		
#define		SPI_SCR_SOFTRESET_NUMB				1		
#define		SPI_SCR_SOFTRESET_RES_VAL			0x0		
//R/W						

#define		SPI_SCR_AUTOIDLE_POS				0		
#define		SPI_SCR_AUTOIDLE_NUMB				1		
#define		SPI_SCR_AUTOIDLE_RES_VAL			0x0		
//R						

//SPI_SSR						
//-------------------						
#define		SPI_SSR_REG		REG32(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET)		


#define		SPI_SSR_RESERVED_POS				1		
#define		SPI_SSR_RESERVED_NUMB				31		
#define		SPI_SSR_RESERVED_RES_VAL			0x00000000		
//R						

#define		SPI_SSR_RESETDONE_POS				0		
#define		SPI_SSR_RESETDONE_NUMB				1		
#define		SPI_SSR_RESETDONE_RES_VAL			0x0		
//R						



//SPI_ISR						
//-------------------						
#define		SPI_ISR_REG		REG32(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET)		


#define		SPI_ISR_RESERVED_POS				5		
#define		SPI_ISR_RESERVED_NUMB				27		
#define		SPI_ISR_RESERVED_RES_VAL			0x0000000		
//R						

#define		SPI_ISR_WAKEUP_POS					4		
#define		SPI_ISR_WAKEUP_NUMB					1		
#define		SPI_ISR_WAKEUP_RES_VAL				0x0		
//R/W						

#define		SPI_ISR_TX_UNDERFLOW_POS			3		
#define		SPI_ISR_TX_UNDERFLOW_NUMB			1		
#define		SPI_ISR_TX_UNDERFLOW_RES_VAL		0x0		
//R/W						

#define		SPI_ISR_RX_OVERFLOW_POS				2		
#define		SPI_ISR_RX_OVERFLOW_NUMB			1		
#define		SPI_ISR_RX_OVERFLOW_RES_VAL			0x0		
//R/W						

#define		SPI_ISR_WE_POS						1		
#define		SPI_ISR_WE_NUMB						1		
#define		SPI_ISR_WE_RES_VAL					0x0		
//R/W						

#define		SPI_ISR_RE_POS						0		
#define		SPI_ISR_RE_NUMB						1		
#define		SPI_ISR_RE_RES_VAL					0x0		
//R/W						



//SPI_IER						
//-------------------						
#define		SPI_IER_REG		REG32(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET)		


#define		SPI_IER_RESERVED_POS				5		
#define		SPI_IER_RESERVED_NUMB				27		
#define		SPI_IER_RESERVED_RES_VAL			0x0000000		
//R						

#define		SPI_IER_MSK4_POS					4		
#define		SPI_IER_MSK4_NUMB					1		
#define		SPI_IER_MSK4_RES_VAL				0x0		
//R/W						

#define		SPI_IER_MSK3_POS					3		
#define		SPI_IER_MSK3_NUMB					1		
#define		SPI_IER_MSK3_RES_VAL				0x0		
//R/W						

#define		SPI_IER_MSK2_POS					2		
#define		SPI_IER_MSK2_NUMB					1		
#define		SPI_IER_MSK2_RES_VAL				0x0		
//R/W						

#define		SPI_IER_MSK1_POS					1		
#define		SPI_IER_MSK1_NUMB					1		
#define		SPI_IER_MSK1_RES_VAL				0x0		
//R/W						

#define		SPI_IER_MSK0_POS					0		
#define		SPI_IER_MSK0_NUMB					1		
#define		SPI_IER_MSK0_RES_VAL				0x0		
//R/W						


//SPI_SET1						
//-------------------						
#define		SPI_SET1_REG		REG32(SPI_BASE_ADDR_ARM+SPI_SET1_OFFSET)		


#define		SPI_SET1_RESERVED_POS				6		
#define		SPI_SET1_RESERVED_NUMB				26		
#define		SPI_SET1_RESERVED_RES_VAL			0x0000000		
//R						

#define		SPI_SET1_DMA_EN_POS					5		
#define		SPI_SET1_DMA_EN_NUMB				1		
#define		SPI_SET1_DMA_EN_RES_VAL				0x0		
//R/W						

#define		SPI_SET1_PTV_POS					1		
#define		SPI_SET1_PTV_NUMB					4		
#define		SPI_SET1_PTV_RES_VAL				0x0		
//R/W						

#define		SPI_SET1_EN_CLK_POS					0		
#define		SPI_SET1_EN_CLK_NUMB				1		
#define		SPI_SET1_EN_CLK_RES_VAL				0x0		
//R/W						



//SPI_SET2						
//-------------------						
#define		SPI_SET2_REG		REG32(SPI_BASE_ADDR_ARM+SPI_SET2_OFFSET)		


#define		SPI_SET2_RESERVED_POS				16		
#define		SPI_SET2_RESERVED_NUMB				16		
#define		SPI_SET2_RESERVED_RES_VAL			0x0000		
//R						

#define		SPI_SET2_MODE_POS					15		
#define		SPI_SET2_MODE_NUMB					1		
#define		SPI_SET2_MODE_RES_VAL				0x0		
//R/W						

#define		SPI_SET2_CP_POS						10		
#define		SPI_SET2_CP_NUMB					5		
#define		SPI_SET2_CP_RES_VAL					0x00		
//R/W						

#define		SPI_SET2_CE_POS						5		
#define		SPI_SET2_CE_NUMB					5		
#define		SPI_SET2_CE_RES_VAL					0x00		
//R/W						

#define		SPI_SET2_CI_POS						0		
#define		SPI_SET2_CI_NUMB					5		
#define		SPI_SET2_CI_RES_VAL					0x00		
//R/W						



//SPI_CTRL						
//-------------------						
#define		SPI_CTRL_REG		REG32(SPI_BASE_ADDR_ARM+SPI_CTRL_OFFSET)		


#define		SPI_CTRL_RESERVED_POS				10		
#define		SPI_CTRL_RESERVED_NUMB				22		
#define		SPI_CTRL_RESERVED_RES_VAL			0x000000		
//R						

#define		SPI_CTRL_AD_POS						7		
#define		SPI_CTRL_AD_NUMB					3		
#define		SPI_CTRL_AD_RES_VAL					0x0		
//R/W						

#define		SPI_CTRL_NB_POS						2		
#define		SPI_CTRL_NB_NUMB					5		
#define		SPI_CTRL_NB_RES_VAL					0x00		
//R/W						

#define		SPI_CTRL_WR_POS						1		
#define		SPI_CTRL_WR_NUMB					1		
#define		SPI_CTRL_WR_RES_VAL					0x0		
//R/W						

#define		SPI_CTRL_RD_POS						0		
#define		SPI_CTRL_RD_NUMB					1		
#define		SPI_CTRL_RD_RES_VAL					0x0		
//R/W						


//SPI_DSR						
//-------------------						
#define		SPI_DSR_REG		REG32(SPI_BASE_ADDR_ARM+SPI_DSR_OFFSET)		


#define		SPI_DSR_RESERVED_POS				2		
#define		SPI_DSR_RESERVED_NUMB				30		
#define		SPI_DSR_RESERVED_RES_VAL			0x00000000		
//R						

#define		SPI_DSR_TX_EMPTY_POS				1		
#define		SPI_DSR_TX_EMPTY_NUMB				1		
#define		SPI_DSR_TX_EMPTY_RES_VAL			0x1		
//R						

#define		SPI_DSR_RX_FULL_POS					0		
#define		SPI_DSR_RX_FULL_NUMB				1		
#define		SPI_DSR_RX_FULL_RES_VAL				0x0		
//R						

//SPI_TX						
//-------------------						
#define		SPI_TX_REG		REG32(SPI_BASE_ADDR_ARM+SPI_TX_OFFSET)		


#define		SPI_TX_SPI_TX_POS					0		
#define		SPI_TX_SPI_TX_NUMB					32		
#define		SPI_TX_SPI_TX_RES_VAL				0x00000000		
//R/W						
//SPI_TX						
//-------------------						
#define		SPI_RX_REG		REG32(SPI_BASE_ADDR_ARM+SPI_RX_OFFSET)		


#define		SPI_TX_SPI_RX_POS					0		
#define		SPI_TX_SPI_RX_NUMB					32		
#define		SPI_TX_SPI_RX_RES_VAL				0x00000000		


//SPI_TEST						
//-------------------						
#define		SPI_TEST_REG		REG32(SPI_BASE_ADDR_ARM+SPI_TEST_OFFSET)		


#define		SPI_TEST_RESERVED_POS				11		
#define		SPI_TEST_RESERVED_NUMB				21		
#define		SPI_TEST_RESERVED_RES_VAL			0x000000		
//R						

#define		SPI_TEST_RTSPEN_POS					6		
#define		SPI_TEST_RTSPEN_NUMB				5		
#define		SPI_TEST_RTSPEN_RES_VAL				0x00		
//R						

#define		SPI_TEST_RCV_POS					5		
#define		SPI_TEST_RCV_NUMB					1		
#define		SPI_TEST_RCV_RES_VAL				0x0		
//R							

#define		SPI_TEST_WCV_POS					4		
#define		SPI_TEST_WCV_NUMB					1		
#define		SPI_TEST_WCV_RES_VAL				0x0		
//R/W						

#define		SPI_TEST_RTV_POS					3		
#define		SPI_TEST_RTV_NUMB					1		
#define		SPI_TEST_RTV_RES_VAL				0x0		
//R						

#define		SPI_TEST_WTV_POS					2		
#define		SPI_TEST_WTV_NUMB					1		
#define		SPI_TEST_WTV_RES_VAL				0x0		
//R/W						

#define		SPI_TEST_FDO_POS					1		
#define		SPI_TEST_FDO_NUMB					1		
#define		SPI_TEST_FDO_RES_VAL				0x0		
//R/W						

#define		SPI_TEST_TMODE_POS					0		
#define		SPI_TEST_TMODE_NUMB					1		
#define		SPI_TEST_TMODE_RES_VAL				0x0		
	//R/W						



#endif