📄 nand_samsung_k9k1208.h
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//NAND_FLASH_NND_RESVD
//-------------------
#define NAND_FLASH_NND_RESVD REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_RESVD_OFFSET)
//NAND_FLASH_NND_CTRL
//-------------------
#define NAND_FLASH_NND_CTRL REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_CTRL_OFFSET)
#define NAND_FLASH_NND_CTRL_RESERVED_0_POS 18
#define NAND_FLASH_NND_CTRL_RESERVED_0_NUMB 14
#define NAND_FLASH_NND_CTRL_RESERVED_0_RES_VAL 0x0
//R
#define NAND_FLASH_NND_CTRL_PREFETCH_POS 17
#define NAND_FLASH_NND_CTRL_PREFETCH_NUMB 1
#define NAND_FLASH_NND_CTRL_PREFETCH_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_POSTWRITE_POS 16
#define NAND_FLASH_NND_CTRL_POSTWRITE_NUMB 1
#define NAND_FLASH_NND_CTRL_POSTWRITE_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT3_POS 15
#define NAND_FLASH_NND_CTRL_WRITEPROT3_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT3_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN3_POS 14
#define NAND_FLASH_NND_CTRL_CHIPEN3_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN3_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT2_POS 13
#define NAND_FLASH_NND_CTRL_WRITEPROT2_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT2_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN2_POS 12
#define NAND_FLASH_NND_CTRL_CHIPEN2_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN2_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT1_POS 11
#define NAND_FLASH_NND_CTRL_WRITEPROT1_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT1_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN1_POS 10
#define NAND_FLASH_NND_CTRL_CHIPEN1_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN1_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT0_POS 9
#define NAND_FLASH_NND_CTRL_WRITEPROT0_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT0_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN0_POS 8
#define NAND_FLASH_NND_CTRL_CHIPEN0_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN0_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_RESERVED_1_POS 7
#define NAND_FLASH_NND_CTRL_RESERVED_1_NUMB 1
#define NAND_FLASH_NND_CTRL_RESERVED_1_RES_VAL 0x0
//R
#define NAND_FLASH_NND_CTRL_ADDRCNT_POS 5
#define NAND_FLASH_NND_CTRL_ADDRCNT_NUMB 2
#define NAND_FLASH_NND_CTRL_ADDRCNT_RES_VAL 0x00
//R/W
#define NAND_FLASH_NND_CTRL_A8_POS 4
#define NAND_FLASH_NND_CTRL_A8_NUMB 1
#define NAND_FLASH_NND_CTRL_A8_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_BE_POS 3
#define NAND_FLASH_NND_CTRL_BE_NUMB 1
#define NAND_FLASH_NND_CTRL_BE_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_RESERVED_2_POS 2
#define NAND_FLASH_NND_CTRL_RESERVED_2_NUMB 1
#define NAND_FLASH_NND_CTRL_RESERVED_2_RES_VAL 0x0
//R
#define NAND_FLASH_NND_CTRL_ECC_256_POS 1
#define NAND_FLASH_NND_CTRL_ECC_256_NUMB 1
#define NAND_FLASH_NND_CTRL_ECC_256_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_ECC_ON_POS 0
#define NAND_FLASH_NND_CTRL_ECC_ON_NUMB 1
#define NAND_FLASH_NND_CTRL_ECC_ON_RES_VAL 0x0
//R/W
//NAND_FLASH_NND_MASK
//-------------------
#define NAND_FLASH_NND_MASK REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_MASK_OFFSET)
#define NAND_FLASH_NND_MASK_RESERVED_POS 4
#define NAND_FLASH_NND_MASK_RESERVED_NUMB 28
#define NAND_FLASH_NND_MASK_RESERVED_RES_VAL 0x0
//R
#define NAND_FLASH_NND_MASK_MSK_EMPTY_POS 3
#define NAND_FLASH_NND_MASK_MSK_EMPTY_NUMB 1
#define NAND_FLASH_NND_MASK_MSK_EMPTY_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_MASK_MSK_FULL_POS 2
#define NAND_FLASH_NND_MASK_MSK_FULL_NUMB 1
#define NAND_FLASH_NND_MASK_MSK_FULL_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_MASK_MSK_COUNT_POS 1
#define NAND_FLASH_NND_MASK_MSK_COUNT_NUMB 1
#define NAND_FLASH_NND_MASK_MSK_COUNT_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_MASK_MSK_READY_POS 0
#define NAND_FLASH_NND_MASK_MSK_READY_NUMB 1
#define NAND_FLASH_NND_MASK_MSK_READY_RES_VAL 0x0
//R/W
//NAND_FLASH_NND_STATUS
//-------------------
#define NAND_FLASH_NND_STATUS REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_STATUS_OFFSET)
#define NAND_FLASH_NND_STATUS_RESERVED_POS 4
#define NAND_FLASH_NND_STATUS_RESERVED_NUMB 28
#define NAND_FLASH_NND_STATUS_RESERVED_RES_VAL 0x0
//R
#define NAND_FLASH_NND_STATUS_FIFO_EMPTY_POS 3
#define NAND_FLASH_NND_STATUS_FIFO_EMPTY_NUMB 1
#define NAND_FLASH_NND_STATUS_FIFO_EMPTY_RES_VAL 0x1
//R/W1C
#define NAND_FLASH_NND_STATUS_FIFO_FULL_POS 2
#define NAND_FLASH_NND_STATUS_FIFO_FULL_NUMB 1
#define NAND_FLASH_NND_STATUS_FIFO_FULL_RES_VAL 0x0
//R/W1C
#define NAND_FLASH_NND_STATUS_COUNT_ZERO_POS 1
#define NAND_FLASH_NND_STATUS_COUNT_ZERO_NUMB 1
#define NAND_FLASH_NND_STATUS_COUNT_ZERO_RES_VAL 0x1
//R/W1C
#define NAND_FLASH_NND_STATUS_READY_EVENT_POS 0
#define NAND_FLASH_NND_STATUS_READY_EVENT_NUMB 1
#define NAND_FLASH_NND_STATUS_READY_EVENT_RES_VAL 0x0
//R/W1C
//NAND_FLASH_NND_READY
//-------------------
#define NAND_FLASH_NND_READY REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_READY_OFFSET)
#define NAND_FLASH_NND_READY_READY_POS 0
#define NAND_FLASH_NND_READY_READY_NUMB 1
#define NAND_FLASH_NND_READY_READY_RES_VAL 0x1
//R
//NAND_FLASH_NND_COMMAND
//-------------------
#define NAND_FLASH_NND_COMMAND REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_COMMAND_OFFSET)
#define NAND_FLASH_NND_COMMAND_RESERVED_POS 8
#define NAND_FLASH_NND_COMMAND_RESERVED_NUMB 24
#define NAND_FLASH_NND_COMMAND_RESERVED_RES_VAL 0x0
//R
#define NAND_FLASH_NND_COMMAND_COMMAND_POS 0
#define NAND_FLASH_NND_COMMAND_COMMAND_NUMB 8
#define NAND_FLASH_NND_COMMAND_COMMAND_RES_VAL 0x0
//R/W
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