nand_samsung_k9k1208.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
* ============================================================================
*
*            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
*
*   Property of Texas Instruments
*   For Unrestricted Internal Use Only
*   Unauthorized reproduction and/or distribution is strictly prohibited.
*   This product is protected under copyright law and trade secret law as an unpublished work.
*   Created 2004, (C) Copyright 2004 Texas Instruments.  All rights reserved.
*
*    test: NAND flash
*
*    project: NEPTUNE SILICON VALIDATION
*
* =============================================================================*/

#ifndef flash_arm_h
#define flash_arm_h

/* ============================================================================
* INCLUDE FILES 
* =============================================================================*/
#include "test.h"
#include <stdlib>
#include "monolithic_neptune_a9.h"
#include "result.h"
#include "errorcodes.h"

#include "flashintel.h"
#include "mif.h"

/* ============================================================================
* GLOBAL DEFINITIONS
* =============================================================================*/


/* ============================================================================
*  FUNCTIONS PROTOTYPES
* =============================================================================*/


/* Commands values */
#define SAMSUNG_NAND_FLASH_LOCK_SETUP         0x002A
#define SAMSUNG_NAND_FLASH_UNLOCK_1           0x0023
#define SAMSUNG_NAND_FLASH_UNLOCK_2           0x0024

/*zhy add for erase command*/
#define SAMSUNG_NAND_FLASH_BLOCK_ERASE_1           0x0060
#define SAMSUNG_NAND_FLASH_BLOCK_ERASE_2           0x00D0

//zhy add for Read ID command
#define SAMSUNG_NAND_FLASH_READ_ID           0x00900090

//zhy add for Reset command
#define SAMSUNG_NAND_FLASH_RESET           0x00FF00FF

//zhy add for Page program command
#define SAMSUNG_NAND_FLASH_PAGE_PROGRAM_1           0x00800080
#define SAMSUNG_NAND_FLASH_PAGE_PROGRAM_2           0x00100010

//zhy add for Read status command
#define SAMSUNG_NAND_FLASH_READ_STATUS           0x00700070

//zhy add for Read command
#define SAMSUNG_NAND_FLASH_READ_1_A          0x00000000
#define SAMSUNG_NAND_FLASH_READ_1_B          0x00010001
#define SAMSUNG_NAND_FLASH_READ_2            0x00500050

/*end*/


/* Device Labels */
#define INTEL_STRATA_FLASH_L18_256Mb_TOP_DEVICE_ID    0x880D
#define INTEL_STRATA_FLASH_L18_256Mb_NB_BLOCK_64KW	    255
#define INTEL_STRATA_FLASH_L18_256Mb_NB_BLOCK_16KW	    4
#define INTEL_STRATA_FLASH_L18_BLOCK_SIZE_64KW        0x20000    /* in Bytes */
#define INTEL_STRATA_FLASH_L18_BLOCK_SIZE_16KW        0x8000     /* in Bytes */

/* Application Labels */
#define SAMSUNG_NAND_FLASH_ADDRESS       0x04000000		//NAND using EMIFS CS1


/* driver functions */
extern void flash_intel_28f256l18top_read_id(UWORD32 Flash_base_address,UWORD32 * ManufactureId, UWORD32 * DeviceId);
extern WORD16 flash_intel_28f256l18top_unlock_one_block(UWORD32 unlock_address);
extern WORD16 flash_intel_28f256l18top_erase_one_block(UWORD32 erase_address);
//zhy add begin
extern WORD16 NAND_flash_SAMSUNG_K9K1208Q0C_erase_test_a9(UWORD32 erase_address);
//zhy add end

/* Test functions */
extern WORD16 NAND_flash_SAMSUNG_K9K1208Q0C_display_id_a9(void);
extern WORD16 flash_intel_28f256l18top_erase_a9(void);
//extern WORD16 flash_intel_28f256l18top_linear_first_block_a9(void);
extern WORD16 flash_intel_28f256l18top_linear_all_block_a9(void);
extern WORD16 NAND_flash_SAMSUNGl_K9K1208Q0C_copy_sdram_a9(void);

extern UWORD16 test_arm_template(void);


#endif /* test_name_arm_h */ 




#ifndef _NAND_FLASH__H
#define _NAND_FLASH__H

//BEGIN INC GENERATION
//--------------------------------------

//NAND_FLASH_NND
#define 			NAND_FLASH_BASE_ADDR_ARM		0xFFFBCC00
//NAND_FLASH_NND_ADDR_SRC
//-------------------
#define            NAND_FLASH_NND_ADDR_SRC                                                                             REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_ADDR_SRC_OFFSET)


#define            NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_POS                                                              0
#define            NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_NUMB                                                             32
#define            NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_RES_VAL                                                          0x0000
//R/W

//Register Offset
//-------------------
#define            NAND_FLASH_NND_REVISION_OFFSET                                                                      0x00
#define            NAND_FLASH_NND_ACCESS_OFFSET                                                                        0x04
#define            NAND_FLASH_NND_ADDR_SRC_OFFSET                                                                      0x08
#define            NAND_FLASH_NND_RESVD_OFFSET                                                                         0x0C
#define            NAND_FLASH_NND_CTRL_OFFSET                                                                          0x10
#define            NAND_FLASH_NND_MASK_OFFSET                                                                          0x14
#define            NAND_FLASH_NND_STATUS_OFFSET                                                                        0x18
#define            NAND_FLASH_NND_READY_OFFSET                                                                         0x1C
#define            NAND_FLASH_NND_COMMAND_OFFSET                                                                       0x20
#define            NAND_FLASH_NND_COMMAND_SEC_OFFSET                                                                   0x24
#define            NAND_FLASH_NND_ECC_SELECT_OFFSET                                                                    0x28
#define            NAND_FLASH_NND_ECC1_OFFSET                                                                          0x2C
#define            NAND_FLASH_NND_ECC2_OFFSET                                                                          0x30
#define            NAND_FLASH_NND_ECC3_OFFSET                                                                          0x34
#define            NAND_FLASH_NND_ECC4_OFFSET                                                                          0x38
#define            NAND_FLASH_NND_ECC5_OFFSET                                                                          0x3C
#define            NAND_FLASH_NND_ECC6_OFFSET                                                                          0x40
#define            NAND_FLASH_NND_ECC7_OFFSET                                                                          0x44
#define            NAND_FLASH_NND_ECC8_OFFSET                                                                          0x48
#define            NAND_FLASH_NND_ECC9_OFFSET                                                                          0x4C
#define            NAND_FLASH_NND_RESET_OFFSET                                                                         0x50
#define            NAND_FLASH_NND_FIFO_OFFSET                                                                          0x54
#define            NAND_FLASH_NND_FIFOCTRL_OFFSET                                                                      0x58
#define            NAND_FLASH_NND_PSC_CLK_OFFSET                                                                       0x5C
#define            NAND_FLASH_NND_SYSTEST_OFFSET                                                                       0x60
#define            NAND_FLASH_NND_SYSCFG_OFFSET                                                                        0x64
#define            NAND_FLASH_NND_SYSSTATUS_OFFSET                                                                     0x68
#define            NAND_FLASH_NND_FIFOTEST1_OFFSET                                                                     0x6C
#define            NAND_FLASH_NND_FIFOTEST2_OFFSET                                                                     0x70
#define            NAND_FLASH_NND_FIFOTEST3_OFFSET                                                                     0x74
#define            NAND_FLASH_NND_FIFOTEST4_OFFSET                                                                     0x78




//NAND_FLASH_NND_REVISION
//-------------------
#define            NAND_FLASH_NND_REVISION                                                                             REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_REVISION_OFFSET)


#define            NAND_FLASH_NND_REVISION_RESERVED_POS                                                                  8
#define            NAND_FLASH_NND_REVISION_RESERVED_NUMB                                                                 24
#define            NAND_FLASH_NND_REVISION_RESERVED_RES_VAL                                                              0x0
//R

#define            NAND_FLASH_NND_REVISION_NND_REVISION_POS                                                              0
#define            NAND_FLASH_NND_REVISION_NND_REVISION_NUMB                                                             8
#define            NAND_FLASH_NND_REVISION_NND_REVISION_RES_VAL                                                          0x00
//R


//NAND_FLASH_NND_ACCESS
//-------------------
#define            NAND_FLASH_NND_ACCESS                                                                               REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_ACCESS_OFFSET)


#define            NAND_FLASH_NND_ACCESS_NND_ACCESS_POS                                                                  0
#define            NAND_FLASH_NND_ACCESS_NND_ACCESS_NUMB                                                                 32
#define            NAND_FLASH_NND_ACCESS_NND_ACCESS_RES_VAL                                                              0x0000
//R/W