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📄 inth_w.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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//*****************************************************************************************/
// interrupt head file for interruption module .
//*****************************************************************************************/
//include configure the INTH mode such as triger mode , priority, IRQ or FIQ

//first define L1 interrupt register.


#ifndef _INTH_W_H
#define _INTH_W_H

#define  INTH_IRQ_MODE                              0x00       
#define  INTH_FIQ_MODE                              0x01
#define  INTH_FALLING_EDGE                          0x00                        
#define	 INTH_LOW_LEVEL                             0x01
				 
#define SECTION_INDEX 								0x0100				 

	

#define INTH_L1_ITR                                  0xfffecb00
#define INTH_L1_MIR                                  0xfffecb04
#define INTH_L1_SIR_IRQ                              0xfffecb10
#define INTH_L1_SIR_FIQ                              0xfffecb14
#define INTH_L1_CONTROL                              0xfffecb18
#define INTH_L1_ILR_0                                0xfffecb1C 
                   
#define INTH_L1_ILR_1                                0xfffecb20
#define INTH_L1_ILR_2                                0xfffecb24
#define INTH_L1_ILR_3                                0xfffecb28
#define INTH_L1_ILR_4                                0xfffecb2C
#define INTH_L1_ILR_5                                0xfffecb30
#define INTH_L1_ILR_6                                0xfffecb34
#define INTH_L1_ILR_7                                0xfffecb38
#define INTH_L1_ILR_8                                0xfffecb3C
#define INTH_L1_ILR_9                                0xfffecb40
#define INTH_L1_ILR_10                               0xfffecb44
#define INTH_L1_ILR_11                               0xfffecb48
#define INTH_L1_ILR_12                               0xfffecb4C
#define INTH_L1_ILR_13                               0xfffecb50
#define INTH_L1_ILR_14                               0xfffecb54
#define INTH_L1_ILR_15                               0xfffecb58
#define INTH_L1_ILR_16                               0xfffecb5C
#define INTH_L1_ILR_17                               0xfffecb60
#define INTH_L1_ILR_18                               0xfffecb64
#define INTH_L1_ILR_19                               0xfffecb68
#define INTH_L1_ILR_20                               0xfffecb6C
#define INTH_L1_ILR_21                               0xfffecb70
#define INTH_L1_ILR_22                               0xfffecb74
#define INTH_L1_ILR_23                               0xfffecb78
#define INTH_L1_ILR_24                               0xfffecb7C
#define INTH_L1_ILR_25                               0xfffecb80
#define INTH_L1_ILR_26                               0xfffecb84
#define INTH_L1_ILR_27                               0xfffecb88
#define INTH_L1_ILR_28                               0xfffecb8C
#define INTH_L1_ILR_29                               0xfffecb90
#define INTH_L1_ILR_30                               0xfffecb94
#define INTH_L1_ILR_31                               0xfffecb98

#define INTH_L1_SSIR                                 0xfffecb9C
#define INTH_L1_GMR                                  0xfffecbA0


//***********************************************************************************************
// FOLLOWING IS L2
#define INTH_L2_ITR_1                                0xfffe0000

#define INTH_L2_ITR_2                                0xfffe0100
#define INTH_L2_MIR_1                                0xfffe0004
#define INTH_L2_MIR_2                                0xfffe0104

#define INTH_L2_SIR_IRQ                              0xfffe0010
#define INTH_L2_SIR_FIQ                              0xfffe0014
#define INTH_L2_CONTROL                              0xfffe0018
#define INTH_L2_SSIR_1                               0xfffe009C
#define INTH_L2_SSIR_2                               0xfffe019C

#define INTH_L2_STATUS                               0xfffe00A0
#define INTH_L2_OCP_CONF                             0xfffe00A4
#define INTH_L2_REV                                  0xfffe00A8
#define INTH_L2_ILR_0                                0xfffe001C
#define INTH_L2_ILR_1                                0xfffe0020
#define INTH_L2_ILR_2                                0xfffe0024
#define INTH_L2_ILR_3                                0xfffe0028
#define INTH_L2_ILR_4                                0xfffe002C
#define INTH_L2_ILR_5                                0xfffe0030
#define INTH_L2_ILR_6                                0xfffe0034
#define INTH_L2_ILR_7                                0xfffe0038
#define INTH_L2_ILR_8                                0xfffe003C
#define INTH_L2_ILR_9                                0xfffe0040
#define INTH_L2_ILR_10                               0xfffe0044
#define INTH_L2_ILR_11                               0xfffe0048
#define INTH_L2_ILR_12                               0xfffe004C
#define INTH_L2_ILR_13                               0xfffe0050
#define INTH_L2_ILR_14                               0xfffe0054
#define INTH_L2_ILR_15                               0xfffe0058
#define INTH_L2_ILR_16                               0xfffe005C
#define INTH_L2_ILR_17                               0xfffe0060
#define INTH_L2_ILR_18                               0xfffe0064
#define INTH_L2_ILR_19                               0xfffe0068
#define INTH_L2_ILR_20                               0xfffe006C
#define INTH_L2_ILR_21                               0xfffe0070
#define INTH_L2_ILR_22                               0xfffe0074
#define INTH_L2_ILR_23                               0xfffe0078
#define INTH_L2_ILR_24                               0xfffe007C
#define INTH_L2_ILR_25                               0xfffe0080
#define INTH_L2_ILR_26                               0xfffe0084
#define INTH_L2_ILR_27                               0xfffe0088
#define INTH_L2_ILR_28                               0xfffe008C
#define INTH_L2_ILR_29                               0xfffe0090
#define INTH_L2_ILR_30                               0xfffe0094
#define INTH_L2_ILR_31                               0xfffe0098
#define INTH_L2_ILR_32                               0xfffe011C
#define INTH_L2_ILR_33                               0xfffe0120
#define INTH_L2_ILR_34                               0xfffe0124
#define INTH_L2_ILR_35                               0xfffe0128
#define INTH_L2_ILR_36                               0xfffe012C
#define INTH_L2_ILR_37                               0xfffe0130
#define INTH_L2_ILR_38                               0xfffe0134
#define INTH_L2_ILR_39                               0xfffe0138
#define INTH_L2_ILR_40                               0xfffe013C
#define INTH_L2_ILR_41                               0xfffe0140
#define INTH_L2_ILR_42                               0xfffe0144
#define INTH_L2_ILR_43                               0xfffe0148
#define INTH_L2_ILR_44                               0xfffe014C
#define INTH_L2_ILR_45                               0xfffe0150
#define INTH_L2_ILR_46                               0xfffe0154
#define INTH_L2_ILR_47                               0xfffe0158
#define INTH_L2_ILR_48                               0xfffe015C
#define INTH_L2_ILR_49                               0xfffe0160
#define INTH_L2_ILR_50                               0xfffe0164
#define INTH_L2_ILR_51                               0xfffe0168
#define INTH_L2_ILR_52                               0xfffe016C
#define INTH_L2_ILR_53                               0xfffe0170
#define INTH_L2_ILR_54                               0xfffe0174
#define INTH_L2_ILR_55                               0xfffe0178
#define INTH_L2_ILR_56                               0xfffe017C
#define INTH_L2_ILR_57                               0xfffe0180
#define INTH_L2_ILR_58                               0xfffe0184
#define INTH_L2_ILR_59                               0xfffe0188
#define INTH_L2_ILR_60                               0xfffe018C
#define INTH_L2_ILR_61                               0xfffe0190
#define INTH_L2_ILR_62                               0xfffe0194
#define INTH_L2_ILR_63                               0xfffe0198

#define INTH_L1_ILR_REG(x)                           (0xfffecb20+(x*4))
#define INTH_L2_ILR_0_31(x)                          (0xfffe001c+(x*4))
#define INTH_L2_ILR_32_63(x)                         (0xfffe011c+(x*4)) 

#define INTH_REQ_FAILED                              0xff
#define INTH_REQ_OK                                  0x00


typedef void  (*isrpointer)();

struct isrParameter {                                                         // this struct perhap is usefule.
                                                                              // if user do not like struct. 
        unsigned int trigerLowLevel;
		unsigned int trigerFallingEdge;                                       // i will not use this.
		unsigned int inthIrqMode;
		unsigned int inthFiqMode;
		unsigned int inthPriority;

}; 

                            
void ConfInterrupt( unsigned int, unsigned int, unsigned int, unsigned int);  // setup one interrupt.
unsigned int GetInthVectorForIRQ( void );                                     // get the interrupt vector.
void OpenInterrupt( unsigned int );
void EnableNewInterrupt( unsigned int );                                      // open one interrupt .
void InterruptInit( );                                                        // initialize all interupt.
void InterruptProcess( unsigned int );
void DisableInerrupt( unsigned  int , unsigned int );                         // user can select disable all interrupt 
                                                                              // and someone interrupt.
void InitializeParameter( );

void OpenInterrupt( unsigned int );                                           // open an interrupt.

unsigned int IsrRegister( unsigned int, isrpointer );                         // register interrupt number.
                 
#endif






























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