kbc.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//*************************************************************************************************/
//                                 COMMIT.INC
//                        FILE NAME: KBC.H
//                        REV      : 0.1
//                        AUTHOR   : ZHANGXUGUANG
//                        DESCRIPTION: DEFINE RELATED REGISTER ADDRESS AND SOME NECESSORY DATA
//  Note: the register's width is 16 bit.                                   
//*************************************************************************************************/
/*
#define KBC_CNTL_REG                               *(unsigned short*)(0xFFFBE000 + 0x00)//R/W
#define KBC_DEBOUNCING_TIME                        *(unsigned short*)(0xFFFBE000 + 0x02)//R/W 
#define KBC_LONGKEY_TIME                           *(unsigned short*)(0xFFFBE000 + 0x04)
#define KBC_TIME_OUT                               *(unsigned short*)(0xFFFBE000 + 0x06)
#define KBC_INTERRUPT_STATUS                       *(unsigned short*)(0xFFFBE000 + 0x08)
#define KBC_CLEAR_INTERRUPT_STATUS                 *(unsigned short*)(0xFFFBE000 + 0x0A)
#define KBC_INTERUPT_ENABLE                        *(unsigned short*)(0xFFFBE000 + 0x0C)
#define KBC_KBR_LATCH                              *(unsigned short*)(0xFFFBE000 + 0x10)
#define KBC_KBC_REG                                *(unsigned short*)(0xFFFBE000 + 0x12)
#define KBC_FULL_CODE_15_0                         *(unsigned short*)(0xFFFBE000 + 0x14)
#define KBC_FULL_CODE_31_16                        *(unsigned short*)(0xFFFBE000 + 0x16)
#define KBC_FULL_CODE_47_32                        *(unsigned short*)(0xFFFBE000 + 0x18)
#define KBC_R0_CONF                                *(unsigned int*)(0xfffe12ac)
#define KBC_R1_CONF                                *(unsigned int*)(0xfffe12b0)
#define KBC_R2_CONF                                *(unsigned int*)(0xfffe12b4)
#define KBC_R3_CONF                                *(unsigned int*)(0xfffe12b8)
#define KBC_R4_CONF                                *(unsigned int*)(0xfffe12bc)
#define KBC_R5_CONF                                *(unsigned int*)(0xfffe12c0)

#define INTERRUPT_L2_MIR_1                         *(unsigned int*)(0xfffe0004)   //mpu level 2 int mir1 register.
#define INTERRUPT_L2_MIR_2                         *(unsigned int*)(0xfffe0104)   //mpu level 2 int mir2 reg.
#define INTERRUPT_L2_CONTROL                       *(unsigned int*)(0xfffe0018)   //mpu level2 int control reg.
#define INTERRUPT_L2_ILR_1                         *(unsigned int*)(0xfffe0020)   //mpu level 2 int ILR 2.


#define INTERRUPT_L1_MIR                           *(unsigned int*)(0xfffecb04)   //mpu level 1 int mir reg.
#define INTERRUPT_L1_CONTROL                       *(unsigned int*)(0xfffecb18)   //mpu level 1 control reg.
#define INTERRUPT_L1_ILR_0                         *(unsigned int*)(0xfffecb1c)   //mpu level 1 ILR reg.
*/
#ifndef _KBC__HH
#define _KBC__HH
#define KBC_CNTL_REG                               (0xFFFBE000 )//R/W
#define KBC_DEBOUNCING_TIME                        (0xFFFBE002 )//R/W 
#define KBC_LONGKEY_TIME                           (0xFFFBE004 )
#define KBC_TIME_OUT                               (0xFFFBE006 )
#define KBC_INTERRUPT_STATUS                       (0xFFFBE008 )
#define KBC_CLEAR_INTERRUPT_STATUS                 (0xFFFBE00a )
#define KBC_INTERUPT_ENABLE                        (0xFFFBE00c )
#define KBC_KBR_LATCH                              (0xFFFBE010 )
#define KBC_KBC_REG                                (0xFFFBE012 )
#define KBC_FULL_CODE_15_0                         (0xFFFBE014 )
#define KBC_FULL_CODE_31_16                        (0xFFFBE016 )
#define KBC_FULL_CODE_47_32                        (0xFFFBE018 )

//above is 16bit
#define KBC_R0_CONF                                (0xfffe12ac)
#define KBC_R1_CONF                                (0xfffe12b0)
#define KBC_R2_CONF                                (0xfffe12b4)
#define KBC_R3_CONF                                (0xfffe12b8)
#define KBC_R4_CONF                                (0xfffe12bc)
#define KBC_R5_CONF                                (0xfffe12c0)

#define INTERRUPT_L2_MIR_1                         (0xfffe0004)   //mpu level 2 int mir1 register.
#define INTERRUPT_L2_MIR_2                         (0xfffe0104)   //mpu level 2 int mir2 reg.
#define INTERRUPT_L2_CONTROL                       (0xfffe0018)   //mpu level2 int control reg.
#define INTERRUPT_L2_ILR_1                         (0xfffe0020)   //mpu level 2 int ILR 2.


#define INTERRUPT_L1_MIR                           (0xfffecb04)   //mpu level 1 int mir reg.
#define INTERRUPT_L1_CONTROL                       (0xfffecb18)   //mpu level 1 control reg.
#define INTERRUPT_L1_ILR_0                         (0xfffecb1c)   //mpu level 1 ILR reg.                              
//*************************************************************************************************/
//define testing function to test the KBC.
//RQ: Response the key press event . power saving, long key, repeat key. first acommpolish the press.
//*************************************************************************************************/

void configureclockofkbc( );                       // configure the KBC colock.
void initkbcinterface( );                          //initialize the kbc interface 
void kbcinthprocess( );                             //identify a key.
void kbcpinconfigure( );                           //configure the pin of kbc module.
void kbcpulluprow( );                              //pull up the kbr line.
void kbcinterruptinit( );    


void kbctest( );

#endif