mcbsp.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================//
//        company:               COMMIT Incorporated                   //
//        department:            HW                                    //
//        author:                LiYuan                                //
//        version:               1.0                                   //
//        create date:           09/13/2005                            //
//        release date:                                                //
//        final revise date:                                           //
//        reviser:                                                     //
//        file descript:                                               //
//=====================================================================//

#include  "MCBSP.h"
#include  "CRPM.h"
#include  "config.h"
#include  "UART_IrDA.h"

//=====================================================================//
//MCBSP initialize                                                     //
//=====================================================================//
void MCBSP_Initialize(int dev_num)
{
MCBSP_Open(dev_num);
MCBSP_IOMultiplex(dev_num);
//MCBSP_I2SModeConfigure(dev_num);
}

//=====================================================================//
//IO multiplex                                                         //
//=====================================================================//
void MCBSP_IOMultiplex(int dev_num)
{
switch(dev_num)
{
  case MCBSP1:
	break;
  case MCBSP_RF:
	break;
  default:
    break;
}
}

//=====================================================================//
//MCBSP open                                                            //
//=====================================================================//
void MCBSP_Open(int dev_num)
{
unsigned char reg_temp;

reg_temp = CLKM13_ARM_IDLECT2_REG;
if((reg_temp & 0x0004) == 0) //ARM_PERCK not enable
  CLKM13_ARM_IDLECT2_REG |= 0x0004; //enable ARM_PERCK

reg_temp = CLKM13_ARM_RSTCT2_REG;
if((reg_temp & 0x0001) == 0) //MPU peripherals not enable
  CLKM13_ARM_RSTCT2_REG |= 0x0001; //enables MPU peripherals

//enable the MCBSP
switch(dev_num)
{
  case MCBSP1:
	break;
  case MCBSP_RF:
	break;
  default:
    break;
}
}

//=====================================================================//
//MCBSP close                                                           //
//=====================================================================//
void MCBSP_Close(int dev_num)
{
switch(dev_num)
{
  case MCBSP1:
	break;
  case MCBSP_RF:
	break;
  default:
    break;
}
}

//=====================================================================//
//MCBSP configure                                                      //
//=====================================================================//
void MCBSP_I2SModeConfigure(int dev_num)
{
int i;

// select ARMPER_CK as MCBSP_ICLK
CONF_MOD_CONF_CTRL_0_REG |= 0x00004000;

// set transimtter, receiver, sample rate generator, frame synchronization generator in reset
MCBSP_SPCR2_REG(dev_num) &= ~0x00c1;
MCBSP_SPCR1_REG(dev_num) &= ~0x0001;

// set synchronization mode, synchronization polarity, clk mode
MCBSP_PCR_REG(dev_num) = 0x000f;

// set data format
MCBSP_RCR2_REG(dev_num) = 0x8060;
MCBSP_RCR1_REG(dev_num) = 0x0060;
MCBSP_XCR2_REG(dev_num) = 0x8060;
MCBSP_XCR1_REG(dev_num) = 0x0060;

// Wait for internal synchronization
for(i = 0; i < 20; i++);

// enable the transimitter and receiver
MCBSP_SPCR2_REG(dev_num) |= 0x0001;
MCBSP_SPCR1_REG(dev_num) |= 0x0001;
}

//=====================================================================//
//MCBSP loop back test                                                 //
//=====================================================================//
void MCBSP_LoopBackTest(int dev_num)
{
int i;
int flag = 0;

short data_rx[2][5] = {0x00, 0x00, 0x00, 0x00, 0x00, \
                       0x00, 0x00, 0x00, 0x00, 0x00,};
short data_tx[2][5] = {0x00, 0xff, 0x55, 0xaa, 0x12, \
                       0x00, 0xff, 0x55, 0xaa, 0x56,};
/*
short data_rx[2][5] = {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, \
                       0x0000, 0x0000, 0x0000, 0x0000, 0x0000,};
short data_tx[2][5] = {0x0000, 0xffff, 0x5555, 0xaaaa, 0x1234, \
                       0x0000, 0xffff, 0x5555, 0xaaaa, 0x5678,};
*/

// select ARMPER_CK as MCBSP_ICLK
CONF_MOD_CONF_CTRL_0_REG |= 0x00004000;

// set transimtter, receiver, sample rate generator, frame synchronization generator in reset
MCBSP_SPCR2_REG(dev_num) &= ~0x00c1;
MCBSP_SPCR1_REG(dev_num) &= ~0x0001;

// set sample rate generator
MCBSP_SRGR2_REG(dev_num) |= 0x2000;
MCBSP_SRGR1_REG(dev_num) |= 0x0000;

// set synchronization mode, synchronization polarity, clk mode
MCBSP_PCR_REG(dev_num) = 0x0f0f;

// set data format
MCBSP_RCR2_REG(dev_num) = 0x0000;
MCBSP_RCR1_REG(dev_num) = 0x0000;
MCBSP_XCR2_REG(dev_num) = 0x0000;
MCBSP_XCR1_REG(dev_num) = 0x0000;

// Wait for internal synchronization
for(i = 0; i < 20; i++);

// enable the transmitter, receiver, sample rate generator, frame sync generator, loop back mode, DX
MCBSP_SPCR2_REG(dev_num) |= 0x00c1;
MCBSP_SPCR1_REG(dev_num) |= 0x8081;

for(i = 0; i < 5; i++)
{
  while(!(MCBSP_SPCR2_REG(dev_num) & 0x0002));
  MCBSP_DXR1_REG(dev_num) = data_tx[0][i];
  MCBSP_DXR2_REG(dev_num) = data_tx[1][i];
  while(!(MCBSP_SPCR1_REG(dev_num) & 0x0002));
  data_rx[0][i] = MCBSP_DRR1_REG(dev_num);
  data_rx[1][i] = MCBSP_DRR2_REG(dev_num);
}

for(i = 0; i < 5; i++)
{
  if((data_rx[0][i] == data_tx[0][i]))// && (data_rx[1][i] == data_tx[1][i]))
    flag++;
}

if(flag == 5)
  UART_Printf(UART2, "\r\n  MCBSP realizes TX and RX perfectly in loop back mode!  \r\n");
else
  UART_Printf(UART2, "\r\n  MCBSP finds %d/100 data error in once loop back test!  \r\n", (5 - flag) * 20);
}