📄 triton_functions.c
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//==============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
// Filename : triton_functions.c
//
// Description : specific functions used for triton validation
//
// Project : Neptune
//
// Author : I.Deville / D. Mendoza / L. Papadopoulos
//
//
// Date of Generation :09/23/2004
//
//===============================================================================
#include "triton_functions.h"
/* ============================================================================
* GLOBAL VARIABLES DECLARATIONS
* =============================================================================*/
UWORD8 SETUP_DONE;
UWORD16 AbbDeviceAddress ; // device address used for the I2c communication
UWORD8 Abb_page_in_use = AbbPageDefault ; // Abb Page selection
UWORD8 flag_receive_end; // Register access ready when reception of the I2c bus
UWORD8 flag_transmit_end; // Register access ready when transmitter of the I2c bus
// Copy from DOLO1
// Extern Variables for test registers
extern UWORD8 USB_REG_LIST[],
MADC_REG_LIST[],
AUX_REG_LIST[],
BCI_REG_LIST[],
VIB_REG_LIST[],
WLED_REG_LIST[],
SIM_CARD_REG_LIST[],
AUDIO_REG_LIST[],
INT2_REG_LIST[],
PMC_MASTER_REG_LIST[],
PMC_SLAVE_REG_LIST[],
RTC_REG_LIST[];
extern UWORD16 USB_REG_LENGTH,
MADC_REG_LENGTH,
AUX_REG_LENGTH,
BCI_REG_LENGTH,
VIB_REG_LENGTH,
WLED_REG_LENGTH,
SIM_CARD_REG_LENGTH,
AUDIO_REG_LENGTH,
INT2_REG_LENGTH,
PMC_MASTER_REG_LENGTH,
PMC_SLAVE_REG_LENGTH,
RTC_REG_LENGTH;
extern char USB_REG_NAME[],
MADC_REG_NAME[],
AUX_REG_NAME[],
BCI_REG_NAME[],
VIB_REG_NAME[],
WLED_REG_NAME[],
SIM_CARD_REG_NAME[],
AUDIO_REG_NAME[],
INT2_REG_NAME[],
PMC_MASTER_REG_NAME[],
PMC_SLAVE_REG_NAME[],
RTC_REG_NAME[];
/* ============================================================================
* TRITON FUNCTIONS
* =============================================================================*/
//---------------------------------------------------------------------
// NAME : Tritonsys_Setup_Done_Write
//
// DESCRIPTION : Set bit value SETUP_DONE
// PARAMETERS : Value 0 or 1
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_Setup_Done_Write(UWORD8 value)
{
int previous_content;
extern UWORD8 SETUP_DONE;
// write SETUP_DONE bit and variable (P protected)
if ( PM_Set_PKEY() == VALID_KEY)
{
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_PB_CFG_TEST);
if (value == 0)
{
MSI2C_MasterPollingSendAbb(PMC_MASTER_PB_CFG_TEST,(previous_content & 0xDF));
}
else
{
MSI2C_MasterPollingSendAbb(PMC_MASTER_PB_CFG_TEST,(previous_content | 0x20));
}
}
SETUP_DONE = value;
// Re-Protect register
MSI2C_MasterPollingSendAbb(PMC_MASTER_PROTECT_PKEY, 0x00);
}
//---------------------------------------------------------------------
// NAME : Tritonsys_PWON_IT_Handle
//
// DESCRIPTION : If PWON IT < 2S --> send DEVLSLEEP , else send DEVOFF
// used for Neptune/Triton PM validation
// PARAMETERS : No
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_PWON_IT_Handle(void)
{
#define LIMIT_CYCLENUMB 0x1000 // variable for wait loop
UWORD16 wait,read_value;
// if short PWON <2s --> DEVSLEEP else DEVOFF
// to access to the page of the Abb module MASTER
// Wait loop 2s
wait = 0;
while(wait < LIMIT_CYCLENUMB);
{
wait++;
}
// check if PWON back high--> DEVSLEEP or low --> DEVOFF
MSI2C_AccessPage(PMC_MASTER_page);
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_STS_HW_CONDITIONS);
if (read_value && STS_HW_PWON) PM_P1_DEVSLP();
else PM_P1_DEVOFF();
}
//---------------------------------------------------------------------
// NAME : Tritonsys_PWON_IT_P1_or_P2_Devoff
//
// DESCRIPTION : If
// PWON low < 2s--> DEVOFF APPLI
// PWON low > 2s--> DEVOFF MODEM
// Used for specificic validation cases where each DEVOFF command must be sent
// in a single test
// PARAMETERS : No
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_PWON_IT_P1_or_P2_Devoff(void)
{
#define LIMIT_CYCLENUMB 0x1000 // variable for wait loop
UWORD16 wait,read_value;
wait = 0;
while(wait < LIMIT_CYCLENUMB);
{
wait++;
}
// check if PWON back high
MSI2C_AccessPage(PMC_MASTER_page);
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_STS_HW_CONDITIONS);
if (read_value && STS_HW_PWON) PM_P2_DEVOFF();
else PM_P1_DEVOFF();
}
//---------------------------------------------------------------------
// NAME : Tritonsys_RPWON_IT_P3_Devoff
//
// DESCRIPTION : If
// RPWON low --> DEVOFF PERIPH
//
// Used for specificic validation cases where each DEVOFF command must be sent
// in a single test
// PARAMETERS : No
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_RPWON_IT_P3_Devoff(void)
{
#define LIMIT_CYCLENUMB 0x1000 // variable for wait loop
UWORD16 wait,read_value;
wait = 0;
while(wait < LIMIT_CYCLENUMB);
{
wait++;
}
MSI2C_AccessPage(PMC_MASTER_page);
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_STS_HW_CONDITIONS);
if (read_value && STS_HW_RPWON) ; // nothing if RPWON high
else PM_P3_DEVOFF(); // if RPWON low
}
//---------------------------------------------------------------------
// NAME : Tritonsys_RPWON_IT_P1_Devoff
//
// DESCRIPTION : If
// RPWON low --> DEVOFF MODEM
//
// Used for specificic validation cases where each DEVOFF command must be sent
// in a single test
// PARAMETERS : No
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_RPWON_IT_P1_Devoff(void)
{
#define LIMIT_CYCLENUMB 0x1000 // variable for wait loop
UWORD16 wait,read_value;
wait = 0;
while(wait < LIMIT_CYCLENUMB);
{
wait++;
}
MSI2C_AccessPage(PMC_MASTER_page);
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_STS_HW_CONDITIONS);
if (read_value && STS_HW_RPWON) ; // nothing if RPWON high
else PM_P1_DEVOFF(); // if RPWON low
}
//---------------------------------------------------------------------
// NAME : Tritonsys_Init
//
// DESCRIPTION : Set default config for Triton in Neptune environment
// I2C init
// PU/PD config
// VRDBB @ 1.4V
// ITWAKEUP unmask
// ITs unmask
// PARAMETERS : No
//
// RETURN VALUE: No
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void Tritonsys_Init(void)
{
int previous_content;
/* I2c interface initialization */
MSI2C_InitConnectionAbb();
/* to access to the page of the Abb module MASTER */
MSI2C_AccessPage(PMC_MASTER_page);
/* configure PU and PD config registers */
/* set MCLK2 PD for non-apps usage */
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_PU_PD_CFG1);
MSI2C_MasterPollingSendAbb(PMC_MASTER_PU_PD_CFG1,(previous_content & 0x02));
/* configure ITWAKEUP1 to be unmasked after 1st switch-on(P1_LVL_WAKEUP=1) */
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_P1_CFG_TRANSITION);
MSI2C_MasterPollingSendAbb(PMC_MASTER_P1_CFG_TRANSITION,(previous_content | 0x80));
/* configure VRDBB @ 1.4V for compatibility with Neptune */
PM_VRDBB_voltage_controled_by_software(VRDBB_1_40v);
/* Enable VBAT comparator : reset bit SEQ_MSK_VBAT_CMP , reg SEQ_CFG_MODE */
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_SEQ_CFG_MODE);
MSI2C_MasterPollingSendAbb(PMC_MASTER_SEQ_CFG_MODE,(previous_content & 0xFD));
/***********************************************************
// SW patch area here
//***********************************************************
//***********************************************************
// patch for bug WEBSID :Triton.BTS_Triton_SI.12
// SUMMARY : Sequence setting VRPLL to 1.4V instead of default 1.05V
// CREATED : 2004-11-26
//***********************************************************
// to access to the page of the Abb module PMC_SLAVE */
MSI2C_AccessPage(PMC_SLAVE_page);
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_SLAVE_VRPLL_CFG_DEDICATED);
MSI2C_MasterPollingSendAbb(PMC_SLAVE_VRPLL_CFG_DEDICATED,(previous_content | 0x11));
/***********************************************************
// SW patch area here
//***********************************************************
//***********************************************************
// patch for bug WEBSID : N/A
// SUMMARY : Sequence for VRDBB current limitation PG1.0
// default value too high, limit current to min
// CREATED : 2004-11-15
//***********************************************************
// to access to the page of the Abb module PMC_SLAVE */
MSI2C_AccessPage(PMC_SLAVE_page);
/* set ILIMN-=11,ILIMN+=11,ILIMP+=111 */
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_SLAVE_VCORE_CFG_TRIM_1);
MSI2C_MasterPollingSendAbb(PMC_SLAVE_VCORE_CFG_TRIM_1,(previous_content | 0xfe));
/***********************************************************
// patch for bug WEBSID : Triton.BTS_Triton_RTL.60
// SUMMARY : Sequence Sleep2Active wrong
// CREATED : 2004-09-20 10:57
//***********************************************************
// 2 SW patch possible : 1st is by patching the seqmem
// 2nd is by preventing IBIAS to go into SLEEP
// Solution 2 programmed here as security to prevent issues when going
// from SLEEP 2 ACTIVE
// to access to the page of the Abb module PMC_SLAVE */
MSI2C_AccessPage(PMC_SLAVE_page);
/* change SLEEP state to ACTIVE state on IBIAS */
previous_content = MSI2C_MasterPollingReceiveAbb(PMC_SLAVE_BIAS_CFG_STATE);
MSI2C_MasterPollingSendAbb(PMC_SLAVE_BIAS_CFG_STATE,(previous_content | 0x0f));
/*********END OF PATCH *************************************/
}
/*---------------------------------------------------------------------
// NAME : Tritonsys_Read_Status
//
// DESCRIPTION : Read Triton status and IT registers to know
// switch-on condition and process INT2
//
// PARAMETERS : No
//
// RETURN VALUE: INT2 Interrupt index
//
// LIMITATIONS : None
//---------------------------------------------------------------------*/
int Tritonsys_Read_Status(void)
{
/* Triton INT sources #*/
#define CHARGE_STOP 0
#define VBUS_PRECHG 1
#define BCI_WATCHDOG 2
#define MADC1 3
#define MADC2 4
#define CARKIT 5
#define SIMCD 6
#define PWON 7
#define RPWON 8
#define VAC 9
#define RTC 10
#define VBATLOW 11
#define VBUS 12
#define HOTDIE 13
#define HOOKDET 14
#define HSDET 15
#define UNKNOWN 99
int state_p1,state_p2,state_p3;
UWORD8 read_value,int2_reg_lsb,int2_reg_msb;
/* to access to the page of the Abb module MASTER */
MSI2C_AccessPage(PMC_MASTER_page);
/* read START_MODE bit (PB_CFG_TEST) to know if start by TESTRESET */
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_PB_CFG_TEST);
read_value = (read_value >> 7) & 0x01;
if (read_value == 1) SERI_Send("TESTRESET start \r\n");
/* read SEQ_P123_STATE to know the current state of each sequencer */
read_value = MSI2C_MasterPollingReceiveAbb(PMC_MASTER_SEQ_P123_STATE);
state_p1 = read_value & 0x03;
state_p2 = (read_value >> 2) & 0x03;
state_p3 = (read_value >> 4) & 0x03;
/* read INT2_P1_STS_A and INT2_P1_STS_B
// to access to the page of the Abb module INT2 */
MSI2C_AccessPage(INT2_page);
int2_reg_lsb = MSI2C_MasterPollingReceiveAbb(INT2_IT2STATUSP1L);
int2_reg_msb = MSI2C_MasterPollingReceiveAbb(INT2_IT2STATUSP1H);
/* to access to the page of the Abb module MASTER */
MSI2C_AccessPage(PMC_MASTER_page);
SERI_Send("\r\nP1 state P2 state P3 state \r\n");
switch(state_p1)
{
case 0x0: SERI_Send("OFF "); break;
case 0x1: SERI_Send("RESERVED ");break;
case 0x2: SERI_Send("SLEEP "); break;
case 0x3: SERI_Send("ACTIVE "); break;
default :
break;
}
switch(state_p2)
{
case 0x0: SERI_Send("OFF "); break;
case 0x1: SERI_Send("RESERVED ");break;
case 0x2: SERI_Send("SLEEP "); break;
case 0x3: SERI_Send("ACTIVE "); break;
default :
break;
}
switch(state_p3)
{
case 0x0: SERI_Send("OFF "); break;
case 0x1: SERI_Send("RESERVED ");break;
case 0x2: SERI_Send("SLEEP "); break;
case 0x3: SERI_Send("ACTIVE "); break;
default :
break;
}
SERI_Send("\r\n");
if ((int2_reg_lsb>>7) && 0x01)
{
SERI_Send("\r\n PWON low detected \r\n");
return(PWON);
}
if ((int2_reg_lsb>>6) && 0x01)
{
SERI_Send("\r\n SIMCD event detected \r\n");
return(SIMCD);
}
if ((int2_reg_lsb>>5) && 0x01)
{
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