crpm.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================//
//        company:               COMMIT Incorporated                   //
//        department:            HW                                    //
//        author:                LiYuan                                //
//        version:               1.0                                   //
//        create date:           09/21/2005                            //
//        release date:                                                //
//        final revise date:                                           //
//        reviser:                                                     //
//        file descript:                                               //
//=====================================================================//

#include  "CRPM.h"
#include  "UART_IrDA.h"

//=====================================================================//
//soft open device                                                     //
//=====================================================================//
void DPLL_Setup(int main_frequency)
{
return;
#if 0
int i;

while(ADPLL1_REG1_REG & 0xc000 != 0xc000); //wait power enable flag and power ok flag to be 1
while((ADPLL1_REG3_REG << 15) == 0); //check if idle flag bit to be 0

CLKM13_ARM_SYSST_REG |= 0x00001000; //choose synchronous scalable mode
CLKM13_ARM_CKCTL_REG |= 0x00000100; //set TC frequency to CK_GEN/4

ADPLL1_REG1_REG = ((short int)(main_frequency/13))<<5; //set arm main frequency

#ifdef _DPLL_SWIMode
  DPLL_SWI();
#else
//enable M latch, N latch, M2 latch and N2 latch
  ADPLL1_REG3_REG &= ~0x4000;
  ADPLL1_REG3_REG |= 0x4000;
  ADPLL1_REG3_REG &= ~0x2000;
  ADPLL1_REG3_REG |= 0x2000;

//soft reset lock sequence initialize
  ADPLL1_REG3_REG |= 0x0080;
  ADPLL1_REG3_REG &= ~0x0080;
  ADPLL1_REG3_REG |= 0x0080;
#endif

for(i=0; i<0xffff; i++);
#endif
}

//=====================================================================//
//soft open device                                                     //
//=====================================================================//
void SoftOpen_Dev(soft_dev_t dev_num)
{
unsigned char reg_temp;

reg_temp = CLKM13_ARM_IDLECT2_REG;
if((reg_temp & 0x0004) == 0) //ARM_PERCK not enable
  CLKM13_ARM_IDLECT2_REG |= 0x0004; //enable ARM_PERCK

reg_temp = CLKM13_ARM_RSTCT2_REG;
if((reg_temp & 0x0001) == 0) //MPU peripherals not enable
CLKM13_ARM_RSTCT2_REG |= 0x0001; //enables MPU peripherals

//enable the UART hardware clock request
switch(dev_num)
{
  case soft_IO:
    ULPDR_SOFT_REQ_REG |= 0x1000;
	break;
  case soft_uWire:
    ULPDR_SOFT_REQ_REG |= 0x0800;
	break;
  case soft_MMC2:
    ULPDR_SOFT_REQ_REG |= 0x0200;
	break;
  case soft_MMC:
    ULPDR_SOFT_REQ_REG |= 0x0100;
	break;
  case soft_UART3:
    ULPDR_SOFT_REQ_REG |= 0x0080;
	break;
  case soft_UART2:
    ULPDR_SOFT_REQ_REG |= 0x0040;
	break;
  case soft_UART1:
    ULPDR_SOFT_REQ_REG |= 0x0020;
	break;
  case soft_USBOTG:
    ULPDR_SOFT_REQ_REG |= 0x0010;
	break;
  case soft_USBPVCI:
    ULPDR_SOFT_REQ_REG |= 0x0008;
	break;
  case soft_MCSI:
    ULPDR_SOFT_REQ_REG |= 0x0004;
	break;
  case soft_CAMERA:
    ULPDR_SOFT_REQ_REG |= 0x0002;
	break;
  case soft_APLL:
    ULPDR_SOFT_REQ_REG |= 0x0001;
	break;
  default:
    break;
}
}

//=====================================================================//
//soft close device                                                    //
//=====================================================================//
void SoftClose_Dev(soft_dev_t dev_num)
{
//disable the UART hardware clock request
switch(dev_num)
{
  case soft_IO:
    ULPDR_SOFT_REQ_REG &= ~0x1000;
	break;
  case soft_uWire:
    ULPDR_SOFT_REQ_REG &= ~0x0800;
	break;
  case soft_MMC2:
    ULPDR_SOFT_REQ_REG &= ~0x0200;
	break;
  case soft_MMC:
    ULPDR_SOFT_REQ_REG &= ~0x0100;
	break;
  case soft_UART3:
    ULPDR_SOFT_REQ_REG &= ~0x0080;
	break;
  case soft_UART2:
    ULPDR_SOFT_REQ_REG &= ~0x0040;
	break;
  case soft_UART1:
    ULPDR_SOFT_REQ_REG &= ~0x0020;
	break;
  case soft_USBOTG:
    ULPDR_SOFT_REQ_REG &= ~0x0010;
	break;
  case soft_USBPVCI:
    ULPDR_SOFT_REQ_REG &= ~0x0008;
	break;
  case soft_MCSI:
    ULPDR_SOFT_REQ_REG &= ~0x0004;
	break;
  case soft_CAMERA:
    ULPDR_SOFT_REQ_REG &= ~0x0002;
	break;
  case soft_APLL:
    ULPDR_SOFT_REQ_REG &= ~0x0001;
	break;
  default:
    break;
}
}

//=====================================================================//
//CRPM register reset Value test                                       //
//=====================================================================//
void CRPMRegResetValueTest(void)
{
short ULPDR_COUNTER_32_LSB_REG_RST_VALUE        = 0x0001;
short ULPDR_COUNTER_32_MSB_REG_RST_VALUE        = 0x0000; //reserved[15:4]
short ULPDR_COUNTER_HIGH_FREQ_LSB_REG_RST_VALUE = 0x0001;
short ULPDR_COUNTER_HIGH_FREQ_MSB_REG_RST_VALUE = 0x0000; //reserved[15:6]
short ULPDR_GAUGING_CTRL_REG_RST_VALUE          = 0x0000; //reserved[15:4, 2]
short ULPDR_IT_STATUS_REG_RST_VALUE             = 0x0000; //reserved[15:4]
short ULPDR_SETUP_ULPD1_CELL2_REG_RST_VALUE     = 0x1fff;
short ULPDR_SETUP_ULPD1_CELL3_REG_RST_VALUE     = 0x003f;
short ULPDR_SETUP_ULPD1_CELL4_REG_RST_VALUE     = 0x0000;
short ULPDR_SOFT_REQ_REG_RST_VALUE              = 0x0000; //reserved[15:13, 10]
short ULPDR_STATUS_REQ_REG_RST_VALUE            = 0x0000; //unkown reset value[15:0], reserved[15:4]
short ULPDR_SLEEP_STATUS_REG_RST_VALUE          = 0x0000; //unkown reset value[1:0], reserved[15:2]
short ULPDR_APLL_CTRL_REG_RST_VALUE             = 0x0002; //unkonw reset value[15], reserved[14:3]
short ULPDR_PWR_CTRL_REG_RST_VALUE              = 0x2a34; //reserved[15:14, 12:6, 2:0]
short ULPDR_SOFT_DISABLE_REQ_REG_RST_VALUE      = 0x0000; //reserved[15:3]
short ULPDR_RESET_STATUS_REG_RST_VALUE          = 0x0001; //reserved[15:4]
short ULPDR_REVISION_NUMBER_REG_RST_VALUE       = 0x0000; //TI internal data[7:0], reserved[15:8]
short ULPDR_CLK_IO_CTRL_REG_RST_VALUE           = 0x0002; //reserved[15:10]
short ULPDR_ENA_MEMORY_RETENTION_REG_RST_VALUE  = 0x0000; //reserved[15:2]
short ULPDR_INC_FRAC_REG_RST_VALUE              = 0x0000;
short ULPDR_INC_SIXTEENTH_REG_RST_VALUE         = 0x0000; //reserved[15:12]
short ULPDR_SETUP_FRAME_REG_RST_VALUE           = 0x0000; //reserved[15:5]
short ULPDR_GSM_TIMER_INIT_REG_RST_VALUE        = 0x0000;
short ULPDR_GSM_TIMER_IT_STATUS_REG_RST_VALUE   = 0x0000; //reserved[15:1]
short ULPDR_GSM_TIMER_VALUE_REG_RST_VALUE       = 0x0001;
short ULPDR_GSM_TIMER_CTRL_REG_RST_VALUE        = 0x0002; //reserved[15:2]
short ULPDR_CLOCK_GSM_REG_RST_VALUE             = 0x0000; //reserved[15:1]
short ULPDR_CLOCK_26M_CTRL_REG_RST_VALUE        = 0x0001; //reserved[15:1]

long CLKM13_ARM_CKCTL_REG_RST_VALUE             = 0x00003000; //reserved[31:15]
long CLKM13_ARM_IDLECT1_REG_RST_VALUE           = 0x00000400; //reserved[31:13, 11, 5:3]
long CLKM13_ARM_IDLECT2_REG_RST_VALUE           = 0x00000104; //reserved[31:12, 10:9, 5:4]
long CLKM13_ARM_EWUPCT_REG_RST_VALUE            = 0x0000003f; //reserved[31:6]
long CLKM13_ARM_RSTCT1_REG_RST_VALUE            = 0x00000000; //reserved[31:4]
long CLKM13_ARM_RSTCT2_REG_RST_VALUE            = 0x00000000; //reserved[31:1]
long CLKM13_ARM_SYSST_REG_RST_VALUE             = 0x00000038; //reserved[31:14, 10:7]
long CLKM13_ARM_CKOUT1_REG_RST_VALUE            = 0x00000015; //reserved[31:6]
long CLKM13_ARM_IDLECT3_REG_RST_VALUE           = 0x00000015; //reserved[31:9, 7:6]
long CLKM13_ARM_RETCTL_REG_RST_VALUE            = 0x00000000; //reserved[31:2]

short CLKM2_DSP_CKCTL_REG_RST_VALUE            = 0x0190; //reserved[15:9, 7:2]
short CLKM2_DSP_IDLECT1_REG_RST_VALUE          = 0x0040; //reserved[15:9, 7:3]
short CLKM2_DSP_IDLECT2_REG_RST_VALUE          = 0x0000; //reserved[15:6, 4:3]
short CLKM2_DSP_RSTCT2_REG_RST_VALUE           = 0x0000; //reserved[15:2]
short CLKM2_DSP_SYSST_REG_RST_VALUE            = 0x0030; //reserved[15:14, 10:7]

short ADPLL1_REG0_REG_RST_VALUE                 = 0x0000; //TI internal data[7:0], reserved[13:8]
short ADPLL1_REG1_REG_RST_VALUE                 = 0x0000;
short ADPLL1_REG2_REG_RST_VALUE                 = 0x0000; //reserved[13, 11, 4]
short ADPLL1_REG3_REG_RST_VALUE                 = 0x9488;

long reg_temp_long = 0x00000000;
short reg_temp_short = 0x0000;

reg_temp_short = ULPDR_COUNTER_32_LSB_REG;
ULPDR_COUNTER_32_LSB_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_COUNTER_32_MSB_REG;
ULPDR_COUNTER_32_MSB_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_COUNTER_HIGH_FREQ_LSB_REG;
ULPDR_COUNTER_HIGH_FREQ_LSB_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_COUNTER_HIGH_FREQ_MSB_REG;
ULPDR_COUNTER_HIGH_FREQ_MSB_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_GAUGING_CTRL_REG;
ULPDR_GAUGING_CTRL_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_IT_STATUS_REG;
ULPDR_IT_STATUS_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SETUP_ULPD1_CELL2_REG;
ULPDR_SETUP_ULPD1_CELL2_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SETUP_ULPD1_CELL3_REG;
ULPDR_SETUP_ULPD1_CELL3_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SETUP_ULPD1_CELL4_REG;
ULPDR_SETUP_ULPD1_CELL4_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SOFT_REQ_REG;
ULPDR_SOFT_REQ_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_STATUS_REQ_REG;
ULPDR_STATUS_REQ_REG_RST_VALUE ^= reg_temp_short; //unkown reset value[15:0]
ULPDR_STATUS_REQ_REG_RST_VALUE &= 0x0000;
reg_temp_short = ULPDR_SLEEP_STATUS_REG;
ULPDR_SLEEP_STATUS_REG_RST_VALUE ^= reg_temp_short; //unkown reset value[1:0]
ULPDR_SLEEP_STATUS_REG_RST_VALUE &= 0xfffc;
reg_temp_short = ULPDR_APLL_CTRL_REG;
ULPDR_APLL_CTRL_REG_RST_VALUE ^= reg_temp_short; //unkonw reset value[15]
ULPDR_APLL_CTRL_REG_RST_VALUE &= 0x7fff;
reg_temp_short = ULPDR_PWR_CTRL_REG;
ULPDR_PWR_CTRL_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SOFT_DISABLE_REQ_REG;
ULPDR_SOFT_DISABLE_REQ_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_RESET_STATUS_REG;
ULPDR_RESET_STATUS_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_REVISION_NUMBER_REG;
ULPDR_REVISION_NUMBER_REG_RST_VALUE ^= reg_temp_short; //TI internal data[7:0]
ULPDR_REVISION_NUMBER_REG_RST_VALUE &= 0xff00;
reg_temp_short = ULPDR_CLK_IO_CTRL_REG;
ULPDR_CLK_IO_CTRL_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_ENA_MEMORY_RETENTION_REG;
ULPDR_ENA_MEMORY_RETENTION_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_INC_FRAC_REG;
ULPDR_INC_FRAC_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_INC_SIXTEENTH_REG;
ULPDR_INC_SIXTEENTH_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_SETUP_FRAME_REG;
ULPDR_SETUP_FRAME_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_GSM_TIMER_INIT_REG;
ULPDR_GSM_TIMER_INIT_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_GSM_TIMER_IT_STATUS_REG;
ULPDR_GSM_TIMER_IT_STATUS_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_GSM_TIMER_VALUE_REG;
ULPDR_GSM_TIMER_VALUE_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_GSM_TIMER_CTRL_REG;
ULPDR_GSM_TIMER_CTRL_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_CLOCK_GSM_REG;
ULPDR_CLOCK_GSM_REG_RST_VALUE ^= reg_temp_short;
reg_temp_short = ULPDR_CLOCK_26M_CTRL_REG;
ULPDR_CLOCK_26M_CTRL_REG_RST_VALUE ^= reg_temp_short;

reg_temp_long = CLKM13_ARM_CKCTL_REG;
CLKM13_ARM_CKCTL_REG_RST_VALUE ^= reg_temp_long;
reg_temp_long = CLKM13_ARM_IDLECT1_REG;
CLKM13_ARM_IDLECT1_REG_RST_VALUE ^= reg_temp_long;
reg_temp_long = CLKM13_ARM_IDLECT2_REG;
CLKM13_ARM_IDLECT2_REG_RST_VALUE ^= reg_temp_long;
reg_temp_long = CLKM13_ARM_EWUPCT_REG;
CLKM13_ARM_EWUPCT_REG_RST_VALUE ^= reg_temp_long;
reg_temp_long = CLKM13_ARM_RSTCT1_REG;
CLKM13_ARM_RSTCT1_REG_RST_VALUE ^= reg_temp_long;
reg_temp_long = CLKM13_ARM_RSTCT2_REG;