bootdsp.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#include "dspcode.h"   //This file can only be included once
#include "global_types.h"

//extern void GPIO_Conf_byMPU(void);

    //#pragma DATA_SECTION(DSPCODE_DARAM,".dspcode")
	#pragma DATA_SECTION(DSPCODE_BootVECT,".dspcode")
    #pragma DATA_SECTION(DSPCODE_SARAMcode,".dspcode")
 //   #pragma DATA_SECTION(DSPCODE_SDRAM,".dspcode")
 //   #pragma DATA_SECTION(DSPCODE_SDRAM4,".dspcode")
 //   #pragma DATA_SECTION(DSPCODE_MapBIOS,".dspcode")

void bootdsp(void)
{
    int i,j;

 
    //reset DSP
	while( ((*(UWORD16 *)0xFFFECE10) & 0x0002) )
    	(*(volatile short *)0xFFFECE10) &= ~0x0002;   
  
	//Set DSP Boot mode to API, modified by zhq 
	while( (*(unsigned int *)0xFFFEC918) != 0x0005 )
    	(*(volatile unsigned int *)0xFFFEC918) = 0x0005; 

	// default value for ARM_IDLECT2 = 0x0100 
	// set bit 6 to turn on the api clock 
	// must turn on the api clock to take 
	// api ram out of host only mode , modified by zhq
	while( !((*(UWORD16 *)0xFFFECE08) & 0x0040) )
    	(*(volatile short *)0xFFFECE08) |= 0x0040; 


	// release API reset, modified by zhq
	while( !((*(UWORD16 *)0xFFFECE10) & 0x0004) ) 
    	(*(volatile short *)0xFFFECE10) |= 0x0004; 


    //release reset of peripherals
    while( !((*(UWORD16 *)0xFFFECE14) & 0x0001) )
    	(*(volatile short *)0xFFFECE14) |= 0x0001;
  
    //enable dsp clock
	while( !((*(UWORD16 *)0xFFFECE00) & 0x2000) )
	    (*(volatile short *)0xFFFECE00) |= 0x2000;

    //DSP MMU and Byte Swap, xdwang 
 //   DMMU_initTLB_ByteSwap();


 //zhy add
 /* try to get the api ram out of host only mode */
 // (*(short*)0xFFFEC91c) = 0x0000; 
  
/* Set DSP Boot mode to API */
//  (*(short*)0xFFFEC918) = 0x0005; 

/* default value for ARM_IDLECT2 = 0x0100 */
/* set bit 6 to turn on the api clock */
/* must turn on the api clock to take */
/* api ram out of host only mode */
 // (*(short*)0xFFFECE08) = 0x0140; 

   DSP_MMU();

  
  	//memcpy((void *)DSPCODE_DARAM_start_addr,(void *)DSPCODE_DARAM,sizeof(DSPCODE_DARAM));
	memcpy((void *)DSPCODE_BootVECT_start_addr,(void *)DSPCODE_BootVECT, sizeof(DSPCODE_BootVECT));
	memcpy((void *)DSPCODE_SARAMcode_start_addr,(void *)DSPCODE_SARAMcode, sizeof(DSPCODE_SARAMcode));
//	memcpy((void *)DSPCODE_SDRAM_start_addr,(void *)DSPCODE_SDRAM, sizeof(DSPCODE_SDRAM));
//	memcpy((void *)DSPCODE_SDRAM4_start_addr,(void *)DSPCODE_SDRAM4, sizeof(DSPCODE_SDRAM4));
//	memcpy((void *)DSPCODE_MapBIOS_start_addr,(void *)DSPCODE_MapBIOS, sizeof(DSPCODE_MapBIOS));

	//GPIO_Conf_byMPU();  //test
/*   for (i=0;i<3;i++)
	{
	gpio_dataout_high(1,8);
	for (j=0;j<1000;j++);
	gpio_dataout_low(1,8);
	for (j=0;j<4000;j++);
	}*/
	// release DSP reset 
//	while( !((*(UWORD16 *)0xFFFECE10) & 0x0002) )
//	    *(volatile short *)0xFFFECE10 |= 0x0002;


  
/* release DSP reset */
  (*(short*)0xFFFECE10) = 0x0006;
    {
  		int i, j;
	  	for (i = 0; i < 1000; i++)
  			for (j = 0; j < 1000; j++);
    }

/*    // disable watchdog 
    *(volatile short *)0xE1006808 = 0x00F5;
    *(volatile short *)0xE1006808 = 0x00A0;
//	*(short *)0xE00@IO = 0x0C; 	// Set GDMA free bit (allows ARM API accesses even if
//				   		// DSP generates a bus error which would have prevented
//                                    // this)
	*(short *)0xE1001C00 = 0x0C;
//#define TMCR_MGS3	0x07FE 
//#define TMCR_MM		0x07FF
//  *(short *)TMCR_MGS3@IO = 0x0510;
//  *(short *)TMCR_MM@IO = 0x0000;
	*(short *)0xE1000FFC = 0x0510;
	*(short *)0xE1000FFE = 0x0;

    {
  		int i, j;
	  	for (i = 0; i < 1000; i++)
  			for (j = 0; j < 1000; j++);
    }

*/
//	bspIntC_clear(BSP_INTC_SOURCE_ID_TC_ABORT);
}