dsp_subsystem.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================//
//        company:               COMMIT Incorporated                   //
//        department:            HW                                    //
//        author:                LiYuan                                //
//        version:               1.0                                   //
//        create date:           11/16/2005                            //
//        release date:                                                //
//        final revise date:                                           //
//        reviser:                                                     //
//        file descript:                                               //
//=====================================================================//

#include  "DSP_subsystem.h"
#include  "MPU_subsystem.h"
#include  "inter_connect.h"

extern char DSP_status;

//=====================================================================//
//DSP MMU                                                              //
//Section mode                                                         //
//=====================================================================//
void DSP_MMU()
{
DSPMMU_CNTL_REG |= 0x00000001; // mask DSP MMU reset

DSPMMU_CNTL_REG |= 0x00000002; // enable DSP MMU module

//---------------------------------------------------------------------//
//1M SDRAM: 0x10b00000-0x10bfffff to 1M DSP: 0x00100000-0x001fffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00100000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000000;
DSPMMU_CAM_L_REG = 0x00004008;
//physical address: 0x10b00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x000010b0;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00000000;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;

//---------------------------------------------------------------------//
//1M SDRAM: 0x10c00000-0x10cfffff to 1M DSP: 0x00200000-0x002fffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00200000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000000;
DSPMMU_CAM_L_REG = 0x00008008;
//physical address: 0x10c00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x000010c0;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00000010;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;

//---------------------------------------------------------------------//
//1M SDRAM: 0x10d00000-0x10dfffff to 1M DSP: 0x00300000-0x003fffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00300000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000000;
DSPMMU_CAM_L_REG = 0x0000c008;
//physical address: 0x10d00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x000010d0;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00000020;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;

//---------------------------------------------------------------------//
//1M SDRAM: 0x10e00000-0x10efffff to 1M DSP: 0x00400000-0x004fffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00400000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000001;
DSPMMU_CAM_L_REG = 0x00000008;
//physical address: 0x10e00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x000010e0;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00000030;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;

//---------------------------------------------------------------------//
//1M SDRAM: 0x10f00000-0x11000000 to 1M DSP: 0x00500000-0x005fffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00400000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000001;
DSPMMU_CAM_L_REG = 0x00004008;
//physical address: 0x10e00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x000010f0;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00000040;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;

//---------------------------------------------------------------------//
//1M Viking: 0x08000000-0x08ffffff to 1M DSP: 0x00c00000-0x00cfffff     //
//---------------------------------------------------------------------//
//virtual address: 0x00400000, size: 1M bytes, p bits: preserved(1)
DSPMMU_CAM_H_REG = 0x00000003;
DSPMMU_CAM_L_REG = 0x00000008;
//physical address: 0x10e00000, ap bits: full access(3)
DSPMMU_RAM_H_REG = 0x00000800;
DSPMMU_RAM_L_REG = 0x00000300;
//base value: 0, current_victim: 0
DSPMMU_LOCK_REG = 0x00001850;
//load data to TLB
DSPMMU_LD_TLB_REG = 0x00000001;
}

//=====================================================================//
//switch to DSP                                                        //
//=====================================================================//
void Switch_to_DSP()
{
//release peripherals
OCP_UART2_SSW_MPU_CONF_REG &= ~0x0001;
OCP_MCBSP1_SSW_MPU_CONF_REG &= ~0x0001;
OCP_I2C_1_SSW_MPU_CONF_REG &= ~0x0001;
OCP_I2C_2_SSW_MPU_CONF_REG &= ~0x0001;
OCP_SPI_SSW_MPU_CONF_REG &= ~0x0001;
TIPB_MCSI1_RHSW_MPU_CNF_REG &= ~0x0001;
TIPB_MCSI2_RHSW_MPU_CNF_REG &= ~0x0001;
TIPB_USIM_RHSW_MPU_CNF_REG &= ~0x0001;

DSP_status = 0;

MAILBOX_Write(MAILBOX_MPU2DSP1, 0x0001, 0x0001);

while(!DSP_status);
}