gsample_ccs24_a9.gel

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· GEL 代码 · 共 527 行 · 第 1/2 页

/* 
 * This GEL file is loaded on the command line of Code Composer 
 * The StartUp() function is called every time you start
 * Code Composer.  You can customize this function to
 * initialize wait states or to perform other initialization.
 * 
 * Revisions:
 *      Nov-19-2004   Yoan Hebrard    1st rev for NEPTUNE MCU
 *      Nov-22-2004   JPM/JCV         2nd rev configuration review 
 *      Nov-30-2004   JCV             3rd rev for Thalassa/CCSV2.4
 */

//StartUp()
OnTargetConnect()
{ 
  GEL_OpenWindow("result");

  GEL_MapOff();

  /* Memory mapping */
  GEL_MapReset();
  memorymap_init();
  GEL_MapOn();

  GEL_TextOut("---->>>  End of StartUp() procedure!  <<<----\n","result");

  /* Neptune Setup */
  watchdog_disable();

  /* DSP reset release */
  release_UMA26_reset();

  // Load the EMIF configuration GEL file
  GEL_LoadGel("c:\\CCS\\Gsample_arm9_emif.gel");
  // EMIFF Configuration
	//EMIFF_Setup_DDRAM();
  EMIFF_Setup_SDRRAM(); 

    //EMIFF_Setup_SDRAM();      // ADD TO USE SDR SDRAM  YUBO 05-09-16

  /* Load User Gel Files & execute its startup procedure that will configure the EMIFs */
  //GEL_LoadGel("E:\\gsample\\ccs_gel_files\\arm9_startup_user.gel");
  //user_startup();
  
  // Select emifs_nfcs_1 instead of gpio19 & emifs_ncs_2 instead of GPIO 43
	//ahuo  Select_EMIFS_nCS1_nCS2();
  
  // FPGA EMIFS Conf  
  //nCS3_SRAM_Setup();
  //nCS1_Flash_Setup();
  
  // FPGA EMIFS Conf
  //nCS2_FPGA_Setup();
  
  // Init MMU to download code into SDRAM
 // init_MMU();
  	init_MMU();

   	DPLL_220Mhz();

  GEL_TextOut("---->>>  End of OnTargetConnect() procedure!  <<<----\n","result");
}

menuitem "DPLL"

hotmenu DPLL_220Mhz()
{

    (*(short*)0xFFFECE18) = (*(int *)0xFFFECE18) | 0x1000;
  (*(short*)0xFFFECE00) = (*(int *)0xFFFECE00) | 0x200;
  (*(short*)0xFFFECf02) = 0x0200;

  //(*(short*)0xFFFECf02) = 0x0080;
  //(*(short*)0xFFFECf02) = 0x0100;

/* release DSP reset */  
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) & 0xbfff;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) | 0x4000;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) & 0xdfff;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) | 0x2000;
  GEL_TextOut("dpll setup to 220Mhz\n","result");
  return;
}

hotmenu DPLL_260Mhz()
{

  
/* release DSP reset */
  (*(short*)0xFFFECf02) = 0x0280;
  
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) & 0xbfff;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) | 0x4000;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) & 0xdfff;
  (*(short*)0xFFFECf08) = (*(int *)0xFFFECf08) | 0x2000;
  GEL_TextOut("dpll setup to 260Mhz\n","result");
  return;
}






menuitem "EMIFS"



// Select emifs_nfcs_1 instead of gpio19 & emifs_ncs_2 instead of EMIFS ADD(25)
hotmenu Select_EMIFS_nCS1_nCS2()
{

  (*(int*)0xFFFE11E8) = 0x00000001; // IO_CONFIG_GPIO_19 (0x18 at reset)
  (*(int*)0xFFFE14B8) = 0x00000002; // IO_CONFIG_GPIO_43 (0x18 at reset)
  (*(int*)0xFFFE100C) = 0x0000EAEF; // IO_COMP_MODE (0x0 at reset)	

  GEL_TextOut("EMIFS nCS1 & nCS2 available at Top Level\n","result");

}


hotmenu nCS3_SRAM_Setup()
{

  // SRAM I/F configuration on CS3
  (*(int*)0xFFFECC1C) = 0x00404088;		/* EMIFS CS3 Configuration Register : A/D Multiplexed, 8 RWS, 0 WWS, WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */
  (*(int*)0xFFFECC5C) = 0x00000103;		/* EMIFS CS3 Advanced Configuration Register : ADV hold = 2 Ref_Clk cycles, OE SETUP = 3 */

  GEL_TextOut("SRAM interface configured on CS3\n","result");

  return;
}

hotmenu nCS1_Flash_Setup()
{

  // SRAM I/F configuration on CS3
  (*(int*)0xFFFECC14) = 0x00404088;		/* EMIFS CS1 Configuration Register : A/D Multiplexed, 8 RWS, 0 WWS, WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */
  (*(int*)0xFFFECC54) = 0x00000103;		/* EMIFS CS1 Advanced Configuration Register : ADV hold = 2 Ref_Clk cycles, OE SETUP = 3 */

  GEL_TextOut("NOR Flash interface configured on CS1\n","result");

  return;
}

hotmenu nCS2_FPGA_Setup()
{

  // FPGA I/F configuration on CS2
  (*(int*)0xFFFECC18) = 0x00404088;		/* EMIFS CS2 Configuration Register : A/D Multiplexed, 8 RWS, 0 WWS, WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */
  (*(int*)0xFFFECC58) = 0x00000103;		/* EMIFS CS2 Advanced Configuration Register : ADV hold = 2 Ref_Clk cycles, OE SETUP = 3 */

  GEL_TextOut("FPGA interface configured on CS2\n","result");

  return;
}


menuitem "Tools"

hotmenu BuildLibrary()
{
  /* Load & Build library project */
  GEL_ProjectLoad("G:\\trd\\Etm-Lite\\4_Implementation\\Common\\ccs_gel\\Gsample_arm9_src.pjt");
  GEL_ProjectBuild(); /* Build library if necesary */
}



find_armboot() {

  if((*(int *)0xFFFECC0C & 0x2) == 0x2) {
	GEL_TextOut("ARMBOOT = 1 --> CS3 = 0x0\n","result");
  	return 1;
  } else {
	GEL_TextOut("ARMBOOT = 0 --> CS0 = 0x0\n","result");
  	return 0;
  }
}


access_width_init()
{
  (*(int*)0xFFFEC900) = 0x0003FF2F;  /* two-cycle access width for apif bus */  

  (*(int*)0xFFFECA00) = 0x0000FF22;               /* two-cycle access width for armrhea TIPB private bus */  
  (*(int*)0xFFFED300) = 0x0000FF22;               /* two-cycle access width for armrhea TIPB public bus */
}



hotmenu watchdog_disable()
{
  /* Disable OMAP MPU Watchdog Timer */
  (*(int*)0xFFFEC808) = 0x00F5;
  (*(int*)0xFFFEC808) = 0x00A0;

  /* Disable Neptune 32K Watchdog */
  (*(int*)0xFFFEB048) = 0xAAAA;
  while ( ((*(int *)0xFFFEB034) & 0x10) == 0x10 );
  (*(int*)0xFFFEB048) = 0x5555;
  while ( ((*(int *)0xFFFEB034) & 0x10) == 0x10 );

  GEL_TextOut("MPU & 32K Watchdogs disabled\n","result");
}


hotmenu release_UMA26_reset()
{

/* try to get the api ram out of host only mode */
  (*(short*)0xFFFEC91c) = 0x0000; 
  
/* Set DSP Boot mode to API */
  (*(short*)0xFFFEC918) = 0x0005; 

/* default value for ARM_IDLECT2 = 0x0100 */
/* set bit 6 to turn on the api clock */
/* must turn on the api clock to take */
/* api ram out of host only mode */
  (*(short*)0xFFFECE08) = 0x0140; 

/* release API reset */
  (*(short*)0xFFFECE10) = 0x0004;
  
/* release DSP reset */
  (*(short*)0xFFFECE10) = 0x0006;

  GEL_TextOut("UMA2.6 released from reset\n","result");

}


// ARM boot  => ROM  on CS0 & SRAM on CS3

hotmenu memorymap_init()
{

 
	/* Internal Boot - ARMBOOT=0 - CS0 = 0x0 */
  	GEL_MapAddStr(0x00000000, 0, 0x00006000, "ROM|AS4", 0);  /* CS0 - Internal Boot ROM - 24KB Public ROM */
 /* 	GEL_MapAddStr(0x00006000, 0, 0x00010000, "ROM|AS4", 0); CS0 - Internal Boot ROM - 64KB Secure ROM */
 /* 	GEL_MapAddStr(0x00200000, 0, 0x00004000, "R|W|AS4", 0); CS0 - Secure RAM - 16KB */
 /* 	GEL_MapAddStr(0x00210000, 0, 0x00000010, "R|AS4", 0);   CS0 - Secure Efuse chain 0 - 128 bits */
 /* 	GEL_MapAddStr(0x00210010, 0, 0x00000020, "R|AS4", 0);   CS0 - Secure Efuse chain 1 - 256 bits */
if (0)
{
//Original settings
  	GEL_MapAddStr(0x04000000, 0, 0x02000000, "R|W|AS2", 0);   /* CS1 - NOR Flash - 64MBytes - Thalassa Config 7 */
  	GEL_MapAddStr(0x08000000, 0, 0x00400000, "R|W|AS2", 0);  /* CS2 - SRAM - 4MBytes */
  	GEL_MapAddStr(0x08400000, 0, 0x00000040, "R|W|AS2", 0);  /* CS2 - ETHERNET */
  	GEL_MapAddStr(0x08420000, 0, 0x00000040, "R|W|AS1", 0);  /* CS2 - FPGA */
  	GEL_MapAddStr(0x0C000000, 0, 0x00400000, "R|W|AS4", 0);  /* CS3 - SRAM - 4MBytes */
  	GEL_MapAddStr(0x0E000000, 0, 0x02000000, "R|W|AS2", 0);  /* CS3 - NOR Flash - 64MBytes Mode3*/
  	GEL_MapAddStr(0x10000000, 0, 0x02000000, "R|W|AS4", 0);  /* EMIFF - DDRAM - 32MBytes */
	}
else
{
 //temporary removed W
  	GEL_MapAddStr(0x04000000, 0, 0x02000000, "R|AS2", 0);   /* CS1 - NOR Flash - 64MBytes - Thalassa Config 7 */
  	GEL_MapAddStr(0x08000000, 0, 0x00400000, "R|AS2", 0);  /* CS2 - SRAM - 4MBytes */
  	GEL_MapAddStr(0x08400000, 0, 0x00000040, "R|AS2", 0);  /* CS2 - ETHERNET */
  	GEL_MapAddStr(0x08420000, 0, 0x00000040, "R|AS1", 0);  /* CS2 - FPGA */
  	GEL_MapAddStr(0x0C000000, 0, 0x00400000, "R|AS4", 0);  /* CS3 - SRAM - 4MBytes */