📄 arm926ej-macros.h.s
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B done$l
start$l
COPIER_SUB
MOV pc,r14
end$l
done$l RESTORE 0, 11, store$l
LOCAL_END
MEND
;-----------------------------------------------------------------------------
; Macro: LOVECS_ABORT testexit
;
; Function: Aborts the test unless it is running from HIVECS
;
; Parameters: address to jump to on abort
;
;-----------------------------------------------------------------------------
MACRO
$label LOVECS_ABORT $testexit
$label LDR r1,=0xffff0000
AND r0,pc,r1
CMP r1,r0
BEQ $label.exit
PRINTF "This Test must be run from HIVECS (0xffff0000)\n"
B $testexit
$label.exit
MOV r0,#0
MOV r1,#0
MEND
;-----------------------------------------------------------------------------
; Macro: BADSWPTB_ABORT testexit
;
; Function: Aborts the test if the trickbox AHB monitor is not preloadable
;
; Parameters: address to jump to on abort
;
;-----------------------------------------------------------------------------
MACRO
$label BADSWPTB_ABORT $testexit
$label LDR r2,=AHBCTLADDR
LDR r3,=AHBCTLPRELOAD
LDR r1,=0x55555555
STR r1,[r3] ; do the preload
LDR r0,[r2] ; get contents of sampled ahb reg
CMP r0,r1
BNE $label.fail
LDR r1,=0xaaaaaaaa
STR r1,[r3]
LDR r0,[r2] ; get contents of sampled ahb reg
CMP r0,r1
BEQ $label.pass
$label.fail
PRINTF "This Test requires a trickbox with preloadable AHBCTLreg\n"
B $testexit
$label.pass
MOV r0,#0
MOV r1,#0
MEND
;--------------------------------------------------------------------------
; Macro: <label> Round_Robin_Mode <register>
;
; Function: Changes the cache replacement algorithm to round robin
; mode from the default random mode.
;
; Parameters: <register> : ARM register to be used by macro
;
; Assumptions: ARM926EJ only
;
;--------------------------------------------------------------------------
MACRO
$label Round_Robin_Mode $register
$label
READ_CONTROL_REG $register
ORR $register, $register, #RR_bit
WRITE_CONTROL_REG $register
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Disable_DCache_Streaming $register
;
; Function: Macro which disables DCache streaming
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Disable_DCache_Streaming $register
$label
MRC p15, 0, $register, c15, c0, 0
ORR $register, $register, #DCache_Streaming
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Enable_DCache_Streaming $register
;
; Function: Macro which enables DCache streaming
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
; -----------------------------------------------------------------------------
MACRO
$label Enable_DCache_Streaming $register
$label
MRC p15, 0, $register, c15, c0, 0
BIC $register, $register, #DCache_Streaming
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Disable_ICache_Streaming $register
;
; Function: Macro which disables ICache streaming
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Disable_ICache_Streaming $register
$label
MRC p15, 0, $register, c15, c0, 0
ORR $register, $register, #ICache_Streaming
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Enable_ICache_Streaming $register
;
; Function: Macro which enables ICache streaming
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Enable_ICache_Streaming $register
$label
MRC p15, 0, $register, c15, c0, 0
BIC $register, $register, #ICache_Streaming
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Disable_DCache_Linefilling $register
;
; Function: Macro which disables DCache linefilling
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Disable_DCache_Linefilling $register
$label
MRC p15, 0, $register, c15, c0, 0
ORR $register, $register, #DCache_Linefill
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> ENable_DCache_Linefilling $register
;
; Function: Macro which enables DCache linefilling
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
; ------------------------------------------------------------------------------
MACRO
$label Enable_DCache_Linefilling $register
$label
MRC p15, 0, $register, c15, c0, 0
BIC $register, $register, #DCache_Linefill
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Disable_ICache_Linefilling $register
;
; Function: Macro which disables ICache linefilling
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Disable_ICache_Linefilling $register
$label
MRC p15, 0, $register, c15, c0, 0
ORR $register, $register, #ICache_Linefill
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Enable_ICache_Linefilling $register
;
; Function: Macro which enables ICache linefilling
;
; Parameters: <label> : optional part number/label for macro
; <register> : internal register used by macro
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Enable_ICache_Linefilling $register
$label
MRC p15, 0, $register, c15, c0, 0
BIC $register, $register, #ICache_Linefill
MCR p15, 0, $register, c15, c0, 0
MEND
; ----------------------------------------------------------------------------
; Macro: <label> Lock_DSegments
;
; Function: Macro which locks data cache segments 0-2
;
; Parameters: <label> : optional part number/label for macro;
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Lock_DSegments
$label
LDR r2, =0x00000003
MCR p15, 0, r2, c9, c0, 0
MEND
;------------------------------------------------------------------------------
; Macro: <label> Lock_ISegments
;
; Function: Macro which locks instruction cache segments 0-2
;
; Parameters: <label> : optional part number/label for macro;
;
; Assumptions: ARM926EJ only
;------------------------------------------------------------------------------
MACRO
$label Lock_ISegments
$label
LDR r2, =0x00000003
MCR p15, 0, r2, c9, c0, 1
MEND
MACRO
Lock_Instrution_Segments
LOCAL
LDR r2, =0x80000000
MCR p15, 0, r2, c9, c0, 1 ; start lockdown, I cache, segment 0
LDR r2, =code
B pool1$l
LTORG
pool1$l
ICACHE_ON r0
MCR p15, 0, r2, c7, c13, 1 ; prefetch cache line
code
GBLA data
data SETA 0
WHILE data < 10
add r0, r0, #1
sub r0, r0, #1
data SETA data + 1
WEND
ICACHE_OFF r0
LDR r2, =0x00000001
MCR p15, 0, r2, c9, c0, 1
LDR r2, =0x80000001 ; start lockdown, I cache, segment 1
MCR p15, 0, r2, c9, c0, 1
LDR r2, =code1
B pool2$l
LTORG
pool2$l
ICACHE_ON r0
MCR p15, 0, r2, c7, c13, 1 ; prefetch cache line
code1
data SETA 0
WHILE data < 10
adds r0, r0, #1
subs r0, r0, #1
data SETA data + 1
WEND
ICACHE_OFF r0
LDR r2, =0x00000002
MCR p15, 0, r2, c9, c0, 1
LDR r2, =0x80000002
MCR p15, 0, r2, c9, c0, 1 ; start lockdown, I cache, segment 2
LDR r2, =code2
B pool3$l
LTORG
pool3$l
ICACHE_ON r0
MCR p15, 0, r2, c7, c13, 1 ; prefetch cache line
code2
data SETA 0
WHILE data < 10
adc r0, r0, #1
sbc r0, r0, #1
data SETA data + 1
WEND
ICACHE_OFF r0
LDR r2, =0x00000003 ; end lockdown
MCR p15, 0, r2, c9, c0, 1
LOCAL_END
MEND
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