arm926ej-macros.h.s

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

*******************************************************************************
;*
;* The confidential and proprietary information contained in this file may
;* only be used by a person authorised under and to the extent permitted
;* by a subsisting licensing agreement from ARM Limited.
;*
;*                 (C) COPYRIGHT 2001 ARM Limited.
;*                       ALL RIGHTS RESERVED
;*
;* This entire notice must be reproduced on all copies of this file
;* and copies of this file may only be made by a person if such person is
;* permitted to do so under the terms of a subsisting license agreement
;* from ARM Limited.
;*
;*		ARM926EJ Macros
;*		=================
;*
;*	Origin: ARM926EJ Validation Suite
;*	Author: Dave Butcher 17/03/1999
;*     $Author: kkneebon $
;*   $Revision: 1.16 $
;*	 $Date: Fri Aug 31 15:43:22 2001 $
;*
;*******************************************************************************
;*
;* Description: This INCLUDE file contains ARM926EJ specific MACROS
;*		used by the ARM926EJ validation suites
;*
;*    Contents:	ARM926EJ Specific Macros
;*		IRAM_ON
;*		IRAM_OFF
;*		DRAM_ON
;*		DRAM_OFF
;*		ALL_RAM_ON
;*		ALL_RAM_OFF
;*		BLOCK_COPY
;*		COPY_SUB
;*		FAST_COPY
;*		BOOT_LOAD
;*		LOVECS_ABORT
;*		BADSWPTB_ABORT
;*    Contents:	ARM926EJ Specific Macros
;*		Round_Robin_Mode
;*		Disable_DCache_Streaming 
;*		Enable_DCache_Streaming 
;*		Disable_ICache_Streaming 
;*		Enable_ICache_Streaming 
;*		Disable_DCache_Linefilling
;*		Enable_DCache_Linefilling
;*		Disable_ICache_Linefilling
;*		Enable_ICache_Linefilling
;*		Lock_DSegments
;*		Lock_ISegments
;*		ARM926EJ_MMU_INIT
;*		Clean_DCacheLine_By_Address
;*		ENTER_SYS_MODE
;*		INVALIDATE_UTLB_VA_2
;*		INVALIDATE_UTLB_VA_3
;*		INVALIDATE_UTLB_2
;*		INVALIDATE_UTLB_3
;*		GET_CACHE_INDEX_FROM_VA
;*		ICACHE_LOCKDOWN_WAY
;*		DCACHE_LOCKDOWN_WAY

;-------------------------------------------------------------------------
;  For peace of mind - define some standard places to use when copying
;  code and data around from IRAM to ERAM to DRAM etc.
;-------------------------------------------------------------------------

IRAM_COPY_ROUT	EQU	0x04000000 - 64	; location of IRAM copy routine
					; (assumed be less than 64 bytes in size)
					; Address is referenced from max IRAM size
					; to ensure will always be at the end of
					; the true IRAM size which is aliased.

IRAMTESTCODE	EQU	0x00002000	; An address in IRAM to use for
					; running tests from IRAM

CONTROLCODE	EQU	0x08100000	; A point well beyond DRAM to hold
					; code doing control of IRAM/DRAM

STORECODE	EQU	0x08200000	; Another safe point to store code
					; data being copied from ERAM to
					; IRAM from points that would be
					; masked by IRAM when it is active

		GBLL	FAST_COPY_USED	; Use this variable so that the		
FAST_COPY_USED	SETL	{FALSE}		; fastcopy toolkit is only copied
					; on the first reference
					; ** Make sure the first appearance
					; ** in the code is also the point it
					; ** it is executed in the code

;; Constants used to identify bits in the CP15 Reg1 Control Reg

DRAM_bit	*	0x00001	; Data SRAM Enable bit
IRAM_bit	*	0x00001 ; Instruction SRAM Enable bit

;--------------------------------------------------------------------------------
; Tightly Coupled Region Sizes....

tcmsize_4K	EQU	0x03
tcmsize_8K	EQU	0x04
tcmsize_16K	EQU	0x05
tcmsize_32K	EQU	0x06
tcmsize_64K	EQU	0x07
tcmsize_128K	EQU	0x08
tcmsize_256K	EQU	0x09
tcmsize_512K	EQU	0x0A
tcmsize_1M	EQU	0x0B
tcmsize_2M	EQU	0x0C
tcmsize_4M	EQU	0x0D
tcmsize_8M	EQU	0x0E
tcmsize_16M	EQU	0x0F
tcmsize_32M	EQU	0x10
tcmsize_64M	EQU	0x11
tcmsize_128M	EQU	0x12
tcmsize_256M	EQU	0x13
tcmsize_512M	EQU	0x14
tcmsize_1G	EQU	0x15
tcmsize_2G	EQU	0x16
tcmsize_4G	EQU	0x17

;-------------------------------------------------------------------------
;  These Macros simply use the System-Macros, where the Instruction and
;  Data cache bits within CP15 correspond directly with the IRAM and DRAM
;  control bits.  These Macros exist to make the ARM926EJ Specific tests
;  less obtuse.  (Avoiding use of macros apparently turning on Caches in
;  a processor without a cache.)
;-------------------------------------------------------------------------

; reg0 bits 2 and 14, i & d ram present
; reg9,c1 bit 0 enable bits
;-------------------------------------------------------------------------
; Switch IRAM_ON
;-------------------------------------------------------------------------

   	MACRO
$label	IRAM_ON	$register
$label
	MRC	p15, 0, $register, c9, c1, 1
	ORR	$register, $register, #IRAM_bit
	MCR	p15, 0, $register, c9, c1, 1
	MEND

;-------------------------------------------------------------------------
; Switch IRAM_OFF
;-------------------------------------------------------------------------

   	MACRO
$label	IRAM_OFF $register
$label
	MRC	p15, 0, $register, c9, c1, 1
	BIC	$register, $register, #IRAM_bit
	MCR	p15, 0, $register, c9, c1, 1
	MEND

;-------------------------------------------------------------------------
; Switch DRAM_ON
;-------------------------------------------------------------------------

	MACRO
$label	DRAM_ON	$register
$label
	MRC	p15, 0, $register, c9, c1, 0
	ORR	$register, $register, #DRAM_bit
	MCR	p15, 0, $register, c9, c1, 0
	MEND

;-------------------------------------------------------------------------
; Switch DRAM_OFF
;-------------------------------------------------------------------------

	MACRO
$label	DRAM_OFF $register
$label
	MRC	p15, 0, $register, c9, c1, 0
	BIC	$register, $register, #DRAM_bit
	MCR	p15, 0, $register, c9, c1, 0
	MEND

;-------------------------------------------------------------------------
; Switch ALL_RAM_ON
;-------------------------------------------------------------------------

	MACRO
$label	ALL_RAM_ON $register
$label
	DRAM_ON $register
	IRAM_ON $register
	MEND

;-------------------------------------------------------------------------
; Switch ALL_RAM_OFF
;-------------------------------------------------------------------------

	MACRO
$label	ALL_RAM_OFF $register
$label	
	DRAM_OFF $register
	IRAM_OFF $register
	MEND


;--------------------------------------------------------------------------------
; Set DRAM Base
;--------------------------------------------------------------------------------
		
	MACRO
$label	SET_DRAM_BASE $register, $base_reg
$label
	MRC	p15, 0, $register, c9, c1, 0
	BIC	$register, $register, #0xFF000000
	BIC	$register, $register, #0x00FF0000
	BIC	$register, $register, #0x0000F000
	ORR	$register, $register, $base_reg
	MCR	p15, 0, $register, c9, c1, 0
	MEND

;--------------------------------------------------------------------------------
; SET DRAM BASE REGISTER
;--------------------------------------------------------------------------------
		
	MACRO
$label  WRITE_DRAM_BASE_REG $register
        MCR     p15, 0, $register, c9, c1, 0
        MEND

;--------------------------------------------------------------------------------
; SET IRAM BASE REGISTER
;--------------------------------------------------------------------------------
		
        MACRO
$label  WRITE_IRAM_BASE_REG $register
        MCR     p15, 0, $register, c9, c1, 1
        MEND
	
	
	
;--------------------------------------------------------------------------------
; Macro:	BLOCK_COPY	<source>, <dest>, <size>
;
; Function:	Copies a block of $size bytes to $destination from $source
;
; Parameters:	<source>	source address of block to copy
;		<destination>	destination address of block to copy
;		<size>		size of block to copy in bytes
;
; Assumptions:	source, dest and size must all be word aligned
;--------------------------------------------------------------------------------

		MACRO
$label		BLOCK_COPY $source, $dest, $size
$label		LOCAL
		LDR	r0,=$source
		LDR	r1,=$dest
		LDR	r2,=$size
		
		MOVS	r3,r2,LSR #5
		AND	r2,r2,#31
		BEQ	copy4$l

loop32$l	LDMIA	r0!,{r4-r11}
		STMIA	r1!,{r4-r11}
		SUBS	r3,r3,#1
		BGT	loop32$l

copy4$l		MOVS	r3,r2,LSR #2
		BEQ	done$l
		
loop4$l		LDR	r4,[r0],#4
		STR	r4,[r1],#4
		SUBS	r3,r3,#1
		BGT	loop4$l

done$l		
		LOCAL_END
		MEND

;-----------------------------------------------------------------------------
; Macro:	COPIER_SUB
;
; Function:	Copies a block of size r2 bytes to r1 from r0
;
; On Entry:	r0 - ptr to source data
;		r1 - ptr to dest data
;		r2 - number of bytes to copy
;
; Assumptions:	source, dest and size must all be word aligned
;-----------------------------------------------------------------------------

		MACRO
$label		COPIER_SUB
$label		LOCAL
		MOVS	r3,r2,LSR #5
		AND	r2,r2,#31
		BEQ	copy4$l

loop32$l	LDMIA	r0!,{r4-r11}
		STMIA	r1!,{r4-r11}
		SUBS	r3,r3,#1
		BGT	loop32$l

copy4$l		MOVS	r3,r2,LSR #2
		BEQ	done$l
		
loop4$l		LDR	r4,[r0],#4
		STR	r4,[r1],#4
		SUBS	r3,r3,#1
		BGT	loop4$l

done$l		LOCAL_END
		MEND

;-----------------------------------------------------------------------------
; Macro:	FAST_COPY <source>, <dest>, <size>
;
; Function:	Copies a block of $size to $destination from $source
;
; Parameters:	<source>	source address of block to copy
;		<destination>	destination address of block to copy
;		<size>		size of block to copy in bytes
;
; Assumptions:	source, dest and size must all be word aligned
;
; Operation:	Using LDM/STM instructions the block is copied from
;		$source to $destination
;		Fast copy : copies a quick copy routine into IRAM
;		if not already done then uses that routine to copy
;		code quickly around
;		Currently Assumes : IRAM is enabled.
;
;-----------------------------------------------------------------------------

		MACRO
$label		FAST_COPY $source, $dest, $size
		LOCAL
$label		PRESERVE 0, 11, store$l
		
		[	:LNOT: FAST_COPY_USED
FAST_COPY_USED	SETL	{TRUE}
		
		BLOCK_COPY start$l, IRAM_COPY_ROUT, end$l-start$l
		B	copy$l
start$l
		COPIER_SUB
		MOV	pc,r14
end$l
		]

copy$l		LDR	r0,=$source
		LDR	r1,=$dest
		LDR	r2,=$size
		ADR	r14,return$l
		LDR	pc,=IRAM_COPY_ROUT
return$l	RESTORE	0, 11, store$l
		LOCAL_END
		MEND
		
;-----------------------------------------------------------------------------
; Macro:	BOOT_LOAD
;
; Function:	Copies an region from it's load to its execution address
;
; Parameters:	none
;
; Operation:	Using LDM/STM instructions the block is copied 
;		Block copies a region defined by using the validation option
;		-config boot.cfg from it's load to it's execution address
;		Currently Assumes : IRAM is enabled.
;
;-----------------------------------------------------------------------------

		MACRO
$label		BOOT_LOAD
		LOCAL
$label		PRESERVE 0, 11, store$l
		BLOCK_COPY start$l, IRAM_COPY_ROUT, end$l-start$l

		[	:DEF: CODE_REGION
		; copy Code execution region
		IMPORT	|Load$$Code$$Base|
		IMPORT	|Image$$Code$$Base|
		IMPORT	|Image$$Code$$Length|

		LDR	r0,=|Load$$Code$$Base|
		LDR	r1,=|Image$$Code$$Base|
		LDR	r2,=|Image$$Code$$Length|
		ADR	r14,code_ret$l
		LDR	pc,=IRAM_COPY_ROUT
code_ret$l
		]
		[	:DEF: DATA_REGION
		; copy Data execution region
		IMPORT	|Load$$Data$$Base|
		IMPORT	|Image$$Data$$Base|
		IMPORT	|Image$$Data$$Length|

		LDR	r0,=|Load$$Data$$Base|
		LDR	r1,=|Image$$Data$$Base|
		LDR	r2,=|Image$$Data$$Length|
		ADR	r14,data_ret$l
		LDR	pc,=IRAM_COPY_ROUT
data_ret$l