inth.h

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 517 行 · 第 1/2 页

/*===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename       	: inth.h

   Description    	: Header file for the ARM Interrupt handler

   Project        	: omap3

   Author         	: Francis Huguenin [e-mail]
   Modified for omap3 by Arnaud Balmelle ([e-mail])
   - Modified interrupt configuration for omap3
   - Modified bit definition of Interrupt Level Register for omap3 (some fields have been swapped)
   - Removed all references to registers INTH_SOURCE_IRQ and INTH_SOURCE_FIQ
   Modified by Greg EDGAR ([e-mail]) 01/21/2000
   - Modified DMA channel numbering from 1-based to 0-based.

   FUNCTIONS PROVIDED    
       INTH_InitDefaultIT: Initialize all the satustar incoming interrupts
       INTH_InitLevel    : Add an interrupt into the Interrupt Level Registers
       INTH_Init         : Initialize the whole given interrupt Level Registers
       INTH_ResetIT      : Reset all the pending IT
       INTH_MASK         : Get the mask value of a given interruption
       INTH_PENDING_INT  : Get the pending interrupts excluding the active IT
       INTH_EnableOneIt  : Unmask the selected interrupt
       INTH_DisableOneIt : Mask the selected interrupt
       INTH_EnableAllIt  : Unmask all the interrupts
       INTH_DisableAllIt : Mask all the interrupts
       INTH_Ack          : Acknowledge an IT and return the interrupt's originator
       INTH_ValidNext    : Validate the next interrupt
       INTH_GetPending   : get the pending interrupts 
===============================================================================
*/
#ifndef _INTH__HH
#define _INTH__HH

#include "global_types.h"

/* ARMINTH_ENHANCED_CNTL_REG register */
#define ARMINTH_BASE_ADDR_ARM     0xFFFECB00
#define ARMINTH_ENHANCED_CNTL_REG_OFFSET 0xA0
#define ARMINTH_ENHANCED_CNTL_REG REG32(ARMINTH_BASE_ADDR_ARM+ARMINTH_ENHANCED_CNTL_REG_OFFSET)


/* 
--------------------------------------------------------------------------
         OFFSET  OF  THE  32 bits REGISTERS          
--------------------------------------------------------------------------
*/
#define INTH_IT_REG_OFFSET             0x00 /* Interrupt register offset */ 
#define INTH_MASK_IT_REG_OFFSET        0x04 /* Mask Interrupt register offset */
#define INTH_SOURCE_IRQ_REG_OFFSET     0x08 /* Srce Binary coded IRQ register offset */
#define INTH_SOURCE_FIQ_REG_OFFSET     0x0C /* Srce Binary coded FIQ register offset */
#define INTH_SOURCE_BIN_IRQ_REG_OFFSET 0x10 /* Srce Binary coded IRQ register offset */
#define INTH_SOURCE_BIN_FIQ_REG_OFFSET 0x14 /* Srce Binary coded FIQ register offset */
#define INTH_CTRL_REG_OFFSET           0x18 /* Control register offset */
#define INTH_IT_LEVEL_REG_OFFSET       0x1C /* Interrupt Level registers offset */

/* 
-------------------------------------------------------------------
                        IT_REGISTER 
 Contains the pending requests
 READ ONLY and RESET and Clear 
--------------------------------------------------------------------
*/
#define INTH_IT_REG_USER_ADDR                    ( MEM_INTH_USER_ADDR       + INTH_IT_REG_OFFSET )
#define INTH_IT_REG_SUPERVISOR_ADDR  	         ( MEM_INTH_SUPERVISOR_ADDR + INTH_IT_REG_OFFSET )

#define INTH_IT_REG_RESET_VALUE	                 0x0

/* READ / WRITE */
#define INTH_MASK_IT_REG_USER_ADDR               ( INTH_IT_REG_USER_ADDR + INTH_MASK_IT_REG_OFFSET )
#define INTH_MASK_IT_REG_SUPERVISOR_ADDR         ( INTH_IT_REG_SUPERVISOR_ADDR + INTH_MASK_IT_REG_OFFSET )

#define INTH_MASK_IT_REG_RESET_VALUE             0xFFFFFFFF

/* 
-------------------------------------------------------------------
                      INTERRUPT LEVEL REGISTERS 
 define all the interrupt and their respective attributes 
 - Kind of IT    : either IFQ or IRQ
 - Priority      : Priority level to process the request
 - Sensitive Edge: Either Falling Edge or Low Level Sensitive
 READ/WRITE
--------------------------------------------------------------------
*/
#define INTH_IT_LEVEL_REG_SUPERVISOR_ADDR ( MEM_INTH_SUPERVISOR_ADDR + INTH_IT_LEVEL_REG_OFFSET )
#define INTH_IT_LEVEL_REG_USER_ADDR       ( INTH_IT_REG_USER_ADDR + INTH_IT_LEVEL_REG_OFFSET )

#define INTH_IT_LEVEL_MASK                0x3F
#define INTH_IT_LEVEL_RESET_VALUE         0x0

/* READ ONLY */
#define INTH_SOURCE_BIN_IRQ_REG_ADDR     ( INTH_IT_REG_USER_ADDR + INTH_SOURCE_BIN_IRQ_REG_OFFSET )
#define INTH_SOURCE_BIN_IRQ_RESET_VALUE  0x0
#define INTH_SOURCE_BIN_IRQ_MASK         0x1F

#define INTH_SOURCE_BIN_FIQ_REG_ADDR     ( INTH_IT_REG_USER_ADDR + INTH_SOURCE_BIN_FIQ_REG_OFFSET )
#define INTH_SOURCE_BIN_FIQ_RESET_VALUE  0x0
#define INTH_SOURCE_BIN_FIQ_MASK         0x1F

/*
-------------------------------------------------------------------------
  CONTROL REGISTER 
READ/WRITE
-------------------------------------------------------------------------
*/
#define INTH_CTRL_REG_USER_ADDR        ( INTH_IT_REG_USER_ADDR       + INTH_CTRL_REG_OFFSET )
#define INTH_CTRL_REG_SUPERVISOR_ADDR  ( INTH_IT_REG_SUPERVISOR_ADDR + INTH_CTRL_REG_OFFSET )
#define INTH_CTRL_MASK                 0x3
#define INTH_CTRL_RESET_VALUE          0x0



/* 
------------------------------------------------------
Bit definition of  Interrupt  Level  Registers       -
------------------------------------------------------
*/
#define INTH_FIQNIRQ_POSBIT        0
#define INTH_PRIORITY_POSBIT       2
#define INTH_SENSITIVE_EDGE_POSBIT 1

#define INTH_FIQ_MASK            0x0001
#define INTH_PRIORITY_MASK       0x007C
#define INTH_SENSITIVE_EDGE_MASK 0x0002


/* 
-------------------------------------------- 
Bit definition of  INTH Control Register 
--------------------------------------------
*/
#define INTH_NEW_IRQ_AGR_POSBIT  0
#define INTH_NEW_FIQ_AGR_POSBIT  1

/* 
--------------------------------------------------------
Bit definition of IRQ/FIQ INTH source binary registers
--------------------------------------------------------
*/
#define INTH_SRC_NUM_MASK	0x001f

/*
--------------------------------------------
Bit definition of INTH Control register
--------------------------------------------
*/
#define INTH_NEW_IRQ_AGR_MASK    0x0001
#define INTH_NEW_FIQ_AGR_MASK    0x0002


/* 
--------------------------------------------------------------------------
         INTERRUPT  CONFIGURATION         
--------------------------------------------------------------------------
*/
#define INTH_FIQNIRQ_0   0
#define INTH_FIQNIRQ_1   1
#define INTH_FIQNIRQ_2   2
#define INTH_FIQNIRQ_3   3
#define INTH_FIQNIRQ_4   4
#define INTH_FIQNIRQ_5   5
#define INTH_FIQNIRQ_6   6
#define INTH_FIQNIRQ_7   7
#define INTH_FIQNIRQ_8   8
#define INTH_FIQNIRQ_9   9
#define INTH_FIQNIRQ_10 10
#define INTH_FIQNIRQ_11 11
#define INTH_FIQNIRQ_12 12
#define INTH_FIQNIRQ_13 13
#define INTH_FIQNIRQ_14 14
#define INTH_FIQNIRQ_15 15
#define INTH_FIQNIRQ_16 16
#define INTH_FIQNIRQ_17 17
#define INTH_FIQNIRQ_18 18
#define INTH_FIQNIRQ_19 19
#define INTH_FIQNIRQ_20 20
#define INTH_FIQNIRQ_21 21
#define INTH_FIQNIRQ_22 22
#define INTH_FIQNIRQ_23 23
#define INTH_FIQNIRQ_24 24
#define INTH_FIQNIRQ_25 25
#define INTH_FIQNIRQ_26 26
#define INTH_FIQNIRQ_27 27
#define INTH_FIQNIRQ_28 28
#define INTH_FIQNIRQ_29 29
#define INTH_FIQNIRQ_30 30
#define INTH_FIQNIRQ_31 31

/* first external interrupt number FIQNIRQ_0  */
#define INTH_AIRQ_FIRST	INTH_FIQNIRQ_0 
/* last external  interrupt number FIQNIRQ_18 */ 
#define INTH_AIRQ_LAST	INTH_FIQNIRQ_18

/*
---------------------------------------------------
 Highest Priority level to process the request    -
---------------------------------------------------
*/
#define INTH_HIGHEST_PRIORITY  0
#define INTH_LOWEST_PRIORITY   31

/* 
---------------------------------------------------
 Total Number of interrupts                       -
---------------------------------------------------
*/
#define INTH_NUMBER_OF_INTERRUPTS  32

/*
--------------------------------------------------
           INTH_InterruptNumber_t                -
   Interrupt Number identifies the Interruption  -
--------------------------------------------------
 */
typedef enum 
{
  INTH_FIQNIRQ_LEVEL2_FIQ   = INTH_FIQNIRQ_0,
  INTH_FIQNIRQ_LEVEL2_IRQ   = INTH_FIQNIRQ_1,
  INTH_FIQNIRQ_USB1         = INTH_FIQNIRQ_2,
  INTH_FIQNIRQ_USB2         = INTH_FIQNIRQ_3,
  INTH_FIQNIRQ_MCBSP_TX	    = INTH_FIQNIRQ_4, 
  INTH_FIQNIRQ_MCBSP_RX	    = INTH_FIQNIRQ_5,
  INTH_FIQNIRQ_CAMIF	    = INTH_FIQNIRQ_6,
  INTH_EXTERNAL_FIQNIRQ_1   = INTH_FIQNIRQ_7,
  INTH_EXTERNAL_FIQNIRQ_2   = INTH_FIQNIRQ_8,
  INTH_FIQNIRQ_ABORT        = INTH_FIQNIRQ_9,
  INTH_FIQNIRQ_DSP_MAILBOX1 = INTH_FIQNIRQ_10,
  INTH_FIQNIRQ_DSP_MAILBOX2 = INTH_FIQNIRQ_11,
  INTH_FIQNIRQ_HSB_MAILBOX  = INTH_FIQNIRQ_12,
  INTH_FIQNIRQ_RHEA_BRIDGE1 = INTH_FIQNIRQ_13,
  INTH_FIQNIRQ_GPIO         = INTH_FIQNIRQ_14,
  INTH_FIQNIRQ_UART         = INTH_FIQNIRQ_15,
  INTH_FIQNIRQ_TIMER3       = INTH_FIQNIRQ_16,
  INTH_FIQNIRQ_LB_MMU       = INTH_FIQNIRQ_17,
  INTH_FIQNIRQ_HSAB_MMU     = INTH_FIQNIRQ_18,
  INTH_FIQNIRQ_DMA_CH0	    = INTH_FIQNIRQ_19,
  INTH_FIQNIRQ_DMA_CH1      = INTH_FIQNIRQ_20,
  INTH_FIQNIRQ_DMA_CH2      = INTH_FIQNIRQ_21,
  INTH_FIQNIRQ_DMA_CH3      = INTH_FIQNIRQ_22,
  INTH_FIQNIRQ_DMA_CH4      = INTH_FIQNIRQ_23,
  INTH_FIQNIRQ_DMA_CH5      = INTH_FIQNIRQ_24,
  INTH_FIQNIRQ_DMA_CH_LCD   = INTH_FIQNIRQ_25,
  INTH_FIQNIRQ_TIMER1       = INTH_FIQNIRQ_26,
  INTH_FIQNIRQ_WD_TIMER     = INTH_FIQNIRQ_27,
  INTH_FIQNIRQ_RHEA_BRIDGE2 = INTH_FIQNIRQ_28,
  INTH_FIQNIRQ_LOCAL_BUS_IF = INTH_FIQNIRQ_29,
  INTH_FIQNIRQ_TIMER2       = INTH_FIQNIRQ_30,
  INTH_FIQNIRQ_LCD_CTRL     = INTH_FIQNIRQ_31

} INTH_InterruptNumber_t;