uartirda.h

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/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : uartirda_a9.h

   Description          : Header file for the UART IrDA connected to ARM9

   Project              : Perseus

   Author               : Sebastien Sabatier


===============================================================================
*/
#ifndef _UARTIRDA__HH
#define _UARTIRDA__HH

#include "result.h"
#include "global_types.h"
#include "mapping.h"

#define UARTIRDA_ADDR1 UART_MODEM_IRDA_BASE_ADDR_ARM

//======================================================================
//  Offset address of UARTIRDA's registers is mutiply by one   
//======================================================================
#define UARTIRDA_DLL_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x00)   // Divisor Latch Low 
#define UARTIRDA_RHR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x00)   // Receive Buffer Register   (R) 
#define UARTIRDA_THR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x00)   // Transmit Holding Register  (W) 

#define UARTIRDA_IER_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x01)   // Interrupt Enable Register 
#define UARTIRDA_DLH_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x01)   // Divisor Latch High 

#define UARTIRDA_FCR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x02)   // FIFO Control Register (W) 
#define UARTIRDA_IIR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x02) 			// Interrupt identification Register (R) 
#define UARTIRDA_EFR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x02)   // Enhanced Feature Register  

#define UARTIRDA_LCR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x03)   // Line Control Register 

#define UARTIRDA_MCR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x04)   // Modem Control Register  		
#define UARTIRDA_ADR1_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x04)   //  ADR1 Register 
#define UARTIRDA_XON1_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x04)   

#define UARTIRDA_LSR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x05)   // Line Status Register  
#define UARTIRDA_ADR2_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x05)   //  ADR2 Register 
#define UARTIRDA_XON2_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x05)    

#define UARTIRDA_MSR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x06)   // Modem Status Register  
#define UARTIRDA_TCR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x06)   // Trasmission control register 
#define UARTIRDA_XOFF1_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x06)   

#define UARTIRDA_XOFF2_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x07)   
#define UARTIRDA_SPR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x07)   // Trasmission control register 
#define UARTIRDA_TLR_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x07)   // Trigger level register 

#define UARTIRDA_MDR1_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x08)   // Mode Definition Register 

#define UARTIRDA_MDR2_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x09)   //  Mode Definition Register

#define UARTIRDA_SFLSR_OFFSET ALIGNOrNotOn32Bits_from8bits(0x0A)   // Status FIFO Line Status register 
#define UARTIRDA_TXFLL_OFFSET ALIGNOrNotOn32Bits_from8bits(0x0A)   // Transmit Frame Lenght Regiser low 


#define UARTIRDA_TXFLH_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0B)   // Transmit Frame Lenght Register  Hight (W)
#define UARTIRDA_RESUME_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0B)  //Resume register  

#define UARTIRDA_RXFLL_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0C)   // Receive Frame Lenght Regiser low
#define UARTIRDA_SFREGL_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x0C)   // Status FIFO Regiser  Hight (R)

#define UARTIRDA_RXFLH_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0D)   // Receive Frame Lenght Regiser  Hight
#define UARTIRDA_SFREGH_OFFSET  ALIGNOrNotOn32Bits_from8bits(0x0D)   // Status FIFO Regiser  Hight (R)


#define UARTIRDA_DIV16_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0F)   // Div1.6 Register  
#define UARTIRDA_ACREG_OFFSET   ALIGNOrNotOn32Bits_from8bits(0x0F)   // Auxiliary Control Register   

#define UARTIRDA_BLR_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x0E)   // BOF Length Register   
#define UARTIRDA_UASR_OFFSET    ALIGNOrNotOn32Bits_from8bits(0x0E)   // BOF Length Register   

#define UARTIRDA_SCR_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x10)   //Supplemetary Control register  

#define UARTIRDA_SSR_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x11)   //Supplemetary Status register  

#define UARTIRDA_EBLR_OFFSET    ALIGNOrNotOn32Bits_from8bits(0x12)   // new BOF Length Enhance Register   

#define UARTIRDA_OSC_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x13)      

#define UARTIRDA_MVR_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x14)      

#define UARTIRDA_SYSC_OFFSET    ALIGNOrNotOn32Bits_from8bits(0x15)     

#define UARTIRDA_SYSS_OFFSET    ALIGNOrNotOn32Bits_from8bits(0x16)    

#define UARTIRDA_WER_OFFSET     ALIGNOrNotOn32Bits_from8bits(0x17)    
//====================================================================================================
// Address of UARTIRDA's registers  
//====================================================================================================

//  UART Interface Register
//FOR SAMSON ONLY #define UARTIRDA_UIR_REG  *(REGISTER_UWORD8*)  (MAP_UART_UIR_REG+UARTIRDA_UIR_OFFSET)

// Divisor Latch Low 
#define UARTIRDA_DLL_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_DLL_OFFSET)
// Receive Buffer Register   (R)
#define UARTIRDA_RHR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_RHR_OFFSET)
// Transmit Holding Register  (W) 	
#define UARTIRDA_THR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_THR_OFFSET)	



// Interrupt Enable Register 
#define UARTIRDA_IER_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_IER_OFFSET)	
#define UARTIRDA_DLH_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_DLH_OFFSET)	// Divisor Latch High 



#define UARTIRDA_FCR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_FCR_OFFSET)	// FIFO Control Register (W) 
#define UARTIRDA_IIR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+ UARTIRDA_IIR_OFFSET)	// Interrupt identification Register (R) 
#define UARTIRDA_EFR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_EFR_OFFSET)	// Enhanced Feature Register  



#define UARTIRDA_LCR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_LCR_OFFSET)	// Line Control Register 


#define UARTIRDA_MCR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_MCR_OFFSET)	// Modem Control Register  		
#define UARTIRDA_ADR1_REG  *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_ADR1_OFFSET)	//  Xon1/ADR1 Register 
#define UARTIRDA_XON1_REG  *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_XON1_OFFSET)	

#define UARTIRDA_LSR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_LSR_OFFSET)	// Line Status Register  
#define UARTIRDA_ADR2_REG  *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_ADR2_OFFSET)
#define UARTIRDA_XON2_REG  *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_XON2_OFFSET)	

#define UARTIRDA_MSR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_MSR_OFFSET)	// Modem Status Register  
#define UARTIRDA_TCR_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_TCR_OFFSET)	// Trasmission control register 
#define UARTIRDA_XOFF1_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_XOFF1_OFFSET)	 


#define UARTIRDA_TLR_REG    *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_TLR_OFFSET)	// Trigger level register 
#define UARTIRDA_XOFF2_REG  *(REGISTER_UWORD8*)  (UARTIRDA_ADDR1+UARTIRDA_XOFF2_OFFSET)	 


#define UARTIRDA_MDR1_REG   *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+UARTIRDA_MDR1_OFFSET)	// Mode Definition Register 


#define UARTIRDA_MDR2_REG   *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_MDR2_OFFSET)	//  Mode Definition Register

#define  UARTIRDA_SFLSR_REG *(REGISTER_UWORD8*) (UARTIRDA_ADDR1+ UARTIRDA_SFLSR_OFFSET)     // Status FIFO Line Status register 
#define UARTIRDA_TXFLL_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_TXFLL_OFFSET)	// Transmit Frame Lenght Regiser low 

#define UARTIRDA_RESUME_REG *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_RESUME_OFFSET)
#define UARTIRDA_TXFLH_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_TXFLH_OFFSET) // Transmit Frame Lenght Regiser  Hight

#define UARTIRDA_SFREGL_REG *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SFREGL_OFFSET) // Status FIFO Regiser  Hight (R)
#define UARTIRDA_RXFLL_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_RXFLL_OFFSET)  // Receive Frame Lenght Regiser low

#define UARTIRDA_SFREGH_REG *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SFREGH_OFFSET) // Status FIFO Regiser  Hight (R)
#define UARTIRDA_RXFLH_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_RXFLH_OFFSET) // Receive Frame Lenght Regiser  Hight


#define UARTIRDA_DIV16_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_DIV16_OFFSET) // Div1.6 Register  
#define UARTIRDA_ACREG_REG  *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_ACREG_OFFSET) // Auxiliary Control Register  

#define UARTIRDA_SCR_REG    *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SCR_OFFSET) //Supplemetary Control register  


#define UARTIRDA_SSR_REG    *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SSR_OFFSET) //Supplemetary Status register  


#define UARTIRDA_BLR_REG    *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_BLR_OFFSET) // BOF Length Register   
#define UARTIRDA_UASR_REG    *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_UASR_OFFSET)

#define UARTIRDA_EBLR_REG   *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_EBLR_OFFSET) // new BOF Length Register   

//6.5 div factor register 
#define UARTIRDA_OSC_REG     *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_OSC_OFFSET) //6.5 division factor register   

#define UARTIRDA_MVR_REG     *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_MVR_OFFSET) 

#define UARTIRDA_SYSC_REG     *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SYSC_OFFSET) 

#define UARTIRDA_SYSS_REG     *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_SYSS_OFFSET) 

#define UARTIRDA_WER_REG     *(REGISTER_UWORD8*)    (UARTIRDA_ADDR1+UARTIRDA_WER_OFFSET) 

// ---- end UARTIRDA configuration  adresse register ---- 

/*
typedef enum {
  THR_W = 0,IER_W,DLL_W,DLH_W,FCR_W,EFR_W,LCR_W,MCR_W,XON1_W,ADDR1_W,XON2_W,ADDR2_W,TCR_W
  ,XOFF1_W,XOFF2_W,SPR_W,TLR_W,MDR1_W,MDR2_W,TXFLL_W,TXFLH_W,RXFLL_W,RXFLH_W,BLR_W
  ,ACREG_W,SCR_W,EBLR_W,SYSC_W,SYSS_W,WER_W
  } register_write_name ;

typedef enum {
  RHR_R = 0,IER_R,DLL_R,DLH_R,IIR_R,EFR_R,LCR_R,MCR_R,XON1_R,ADDR1_R,XON2_R,ADDR2_R,LSR_R
  ,MSR_R,TCR_R,XOFF1_R,XOFF2_R,SPR_R,TLR_R,MDR1_R,MDR2_R,SFLSR_R,RESUME_R,SFREGL_R,SFREGH_R
  ,BLR_R,UASR_R,ACREG_R,SCR_R,SSR_R,EBLR_R,MVR_R,SYSC_R,SYSS_R,WER_R
  } register_read_name ;

UWORD8 Write_category[27] = {
  //THR_W = 0,IER_W,DLL_W,DLH_W,FCR_W,EFR_W,LCR_W,MCR_W,XON1_W,ADDR1_W,XON2_W,ADDR2_W,TCR_W
     1       ,  6  ,  2  ,  2  ,  5  ,  3  ,  1  ,  5  ,  3   ,   3   ,  3   ,   3   ,  4  
  //,XOFF1_W,XOFF2_W,SPR_W,TLR_W,MDR1_W,MDR2_W,TXFLL_W,TXFLH_W,RXFLL_W,RXFLH_W,BLR_W
    ,   3   ,    3  ,  1  ,  4  ,  1   ,  1   ,  1    ,   1   ,   1   ,  1    ,  1  
  //,ACREG_W,SCR_W,EBLR_W,SYSC_W,SYSS_W,WER_W
    ,  1    ,  1  ,   1   ,  1  ,  1   ,  1
     }
UWORD8 Write_category[34] = {
  //RHR_R = 0,IER_R,DLL_R,DLH_R,IIR_R,EFR_R,LCR_R,MCR_R,XON1_R,ADDR1_R,XON2_R,ADDR2_R,LSR_R
       1     ,   6 ,  2  ,  2  ,  1  ,  3  ,  1  ,  5  ,  3   ,   3   ,  3   ,   3   ,  1  
    ,  1, 4 , 3   ,3 
  //,MSR_R,TCR_R,XOFF1_R,XOFF2_R,SPR_R,TLR_R,MDR1_R,MDR2_R,SFLSR_R,RESUME_R,SFREGL_R,SFREGH_R
    ,  1  ,  4  ,   3   ,  3    ,  1  ,  4  ,  1   ,  1   ,  1    ,   1    ,   1    ,  1     
  //,BLR_R,UASR_R,ACREG_R,SCR_R,SSR_R,EBLR_R,MVR_R,SYSC_R,SYSS_R,WER_R
    ,  1  ,  1   ,  1    ,  1  ,  1  ,   1  ,  1  ,  1   ,   1  , 1 
     }
*/

#define SET_LCR7_TO_0     UARTIRDA_LCR_REG &= 0x7F ;
#define SET_LCR7_TO_1     UARTIRDA_LCR_REG |= 0x80 ;
#define UNSET_LCR_0xBF   UARTIRDA_LCR_REG &= 0xFC ;
#define SET_LCR_0xBF     UARTIRDA_LCR_REG = 0xBF ;
#define SET_EFR_4         UARTIRDA_EFR_REG |= 0x10 ;
#define SET_MCR_6         UARTIRDA_MCR_REG |= 0x40 ;
    

typedef enum
{

 UARTIRDA_FCR_REG_RESET_ERROR     = 50,
 UARTIRDA_SCR_REG_RESET_ERROR     = 51,
 UARTIRDA_LCR_REG_RESET_ERROR     = 52,
 UARTIRDA_LSR_REG_RESET_ERROR     = 53,
 UARTIRDA_SSR_REG_RESET_ERROR     = 54,
 UARTIRDA_MCR_REG_RESET_ERROR     = 55,
 UARTIRDA_MSR_REG_RESET_ERROR     = 56,
 UARTIRDA_IER_REG_RESET_ERROR     = 57,
 UARTIRDA_IIR_REG_RESET_ERROR     = 58,
 UARTIRDA_EFR_REG_RESET_ERROR     = 59,   

//XON1/ADDR1,  XON2/ADDR2,  XOFF1, XOFF2, SPR, DLL, DLH UNDEFINED on reset

 UARTIRDA_TCR_REG_RESET_ERROR   = 60,   
 UARTIRDA_TLR_REG_RESET_ERROR   = 61, 
 UARTIRDA_MDR1_REG_RESET_ERROR  = 62, 
 UARTIRDA_MDR2_REG_RESET_ERROR  = 63,   
 UARTIRDA_TXFLL_REG_RESET_ERROR = 64,   
 UARTIRDA_TXFLH_REG_RESET_ERROR = 65,   
 UARTIRDA_RXFLL_REG_RESET_ERROR = 66,   
 UARTIRDA_RXFLH_REG_RESET_ERROR = 67,    


//SFLSR and SFREGL are undefined on reset

 UARTIRDA_RESUME_REG_RESET_ERROR = 68,   
 UARTIRDA_BLR_REG_RESET_ERROR    = 69,     
 UARTIRDA_DIV16_REG_RESET_ERROR  = 70,  
 UARTIRDA_ACREG_RESET_ERROR      = 71,

 UARTIRDA_DLL_INIT_ERROR         = 72, 
 UARTIRDA_DLH_INIT_ERROR         = 73
//FOR SAMSON ONLY  UARTIRDA_UIR_REG_RESET_ERROR    = 74

} UARTIRDA_Error_t;


//------------------------------------------
// UIRD_SetBfToLcr
//------------------------------------------
UWORD8 UIRD_SetBfToLcr(void);


//--------------------------------------------------------------------
// UIRD_ClearLcr7
//--------------------------------------------------------------------
UWORD8 UIRD_ClearLcr7(void);


//--------------------------------------------------------------------
// UIRD_SetEfr4
//--------------------------------------------------------------------
UWORD8 UIRD_SetEfr4(void);


//--------------------------------------------------------------------
// UIRD_RestoreEfr
//--------------------------------------------------------------------
void UIRD_RestoreEfr(const UWORD8 value);


//--------------------------------------------------------------------
// UIRD_SetMcr6
//--------------------------------------------------------------------
UWORD8 UIRD_SetMcr6(void);


//--------------------------------------------------
//    UIRD_RestoreMcr
//--------------------------------------------------
void UIRD_RestoreMcr(const UWORD8 mcr);

	

//--------------------------------------------------------------------------------------
//NAME        : UIRD_InitIer
//DESCRIPTION : Setup the Modem Interrupt Enable Register
//PARAMETERS the values are either 0=>Disable , 1=>Enable
// RxINT   : RHR Interrupt  
// TxINT   : THR Interrupt
// RxStINT : Line Status Interrupt
// ModemINT: Modem Status Register Interrupt
// Sleep   : Sleep mode
// Xoff    : XOFF Interrupt 
// RTSINT  : Output Request To Send Interrupt
// CTSINT  : Input Clear To Send Interrupt
//RETURN VALUE: None
//--------------------------------------------------------------------------------------