mem.h~

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· H~ 代码 · 共 735 行 · 第 1/3 页

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735 行
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#define MEM_RHEA_STROBE0_CS3_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 3  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS4_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 4  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS5_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 5  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS6_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 6  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS7_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 7  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS8_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 8  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS9_ADDR   \        ( MEM_RHEA_STROBE0_CS0_ADDR + 9  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS10_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 10 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS11_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 11 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS12_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 12 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS13_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 13 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS14_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 14 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS15_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 15 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS16_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 16 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS17_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 17 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS18_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 18 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS19_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 19 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS20_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 20 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS21_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 21 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS22_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 22 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS23_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 23 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS24_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 24 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS25_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 25 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS26_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 26 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS27_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 27 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS28_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 28 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS29_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 29 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS30_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 30 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE0_CS31_ADDR  \        ( MEM_RHEA_STROBE0_CS0_ADDR + 31 * MEM_RHEA_STROBE_LENGTH )/*----------------------------------------------------------------------------------*//* Address of strobe1 Chip Select 0 to 23                                           *//*----------------------------------------------------------------------------------*/#define MEM_RHEA_STROBE1_CS0_ADDR  MEM_RHEA_STROBE1_ADDR#define MEM_RHEA_STROBE1_CS1_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR +      MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS2_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 2  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS3_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 3  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS4_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 4  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS5_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 5  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS6_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 6  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS7_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 7  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS8_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 8  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS9_ADDR  \        ( MEM_RHEA_STROBE1_CS0_ADDR + 9  * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS10_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 10 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS11_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 11 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS12_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 12 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS13_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 13 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS14_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 14 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS15_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 15 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS16_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 16 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS17_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 17 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS18_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 18 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS19_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 19 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS20_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 20 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS21_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 21 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS22_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 22 * MEM_RHEA_STROBE_LENGTH )#define MEM_RHEA_STROBE1_CS23_ADDR \        ( MEM_RHEA_STROBE1_CS0_ADDR + 23 * MEM_RHEA_STROBE_LENGTH )/*--------------------------------------------------------------------------*//* CONFIGURATION  REGISTER  MAPPING ONLY ACCESSIBLE IN PRIVILEGE  MODE      *//*--------------------------------------------------------------------------*/#define BASE_ADDRESS_INT_PERI  0xFFFEC000#define MEM_SIZE_IN_BYTES 0x100 /* 256 bytes */#define MEM_LCD_CONTROLLER_SUPERVISOR_ADDR      BASE_ADDRESS_INT_PERI#define MEM_LOCALBUS_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  1 * MEM_SIZE_IN_BYTES )#define MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  2 * MEM_SIZE_IN_BYTES )#define MEM_HSAB_INTERFACE_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  3 * MEM_SIZE_IN_BYTES )#define MEM_HSAB_MMU_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  4 * MEM_SIZE_IN_BYTES )#define MEM_TIMER_1_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  5 * MEM_SIZE_IN_BYTES )#define MEM_TIMER_2_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  6 * MEM_SIZE_IN_BYTES )#define MEM_TIMER_3_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  7 * MEM_SIZE_IN_BYTES )#define MEM_WATCH_DOG_TIMER_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  8 * MEM_SIZE_IN_BYTES )#define MEM_API_INTERFACE_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  9 * MEM_SIZE_IN_BYTES )#define MEM_RHEA_BRIDGE_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  10 * MEM_SIZE_IN_BYTES )#define MEM_INTH_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  11 * MEM_SIZE_IN_BYTES )#define MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  12 * MEM_SIZE_IN_BYTES )/* Reserved */#define MEM_CLKM_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  14 * MEM_SIZE_IN_BYTES )#define MEM_DPLL1_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  15 * MEM_SIZE_IN_BYTES )#define MEM_DPLL2_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  16 * MEM_SIZE_IN_BYTES )#define MEM_DPLL3_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  17 * MEM_SIZE_IN_BYTES )#define MEM_DSP_MMU_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  18 * MEM_SIZE_IN_BYTES )#define MEM_RHEA_BRIDGE2_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  19 * MEM_SIZE_IN_BYTES )#define MEM_JTAG_ID_CODE_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  20 * MEM_SIZE_IN_BYTES )/* Reserved */#define MEM_DMA_CONTROLLER_SUPERVISOR_ADDR \        ( BASE_ADDRESS_INT_PERI +  24 * MEM_SIZE_IN_BYTES )/*--------------------------------------------------------------------------*//* INTERNAL PERIPHERAL MAPPING USER MODE                                    *//*--------------------------------------------------------------------------*/#define MEM_USER_MODE_OFFSET 0x0000#define MEM_LCD_CONTROLLER_USER_ADDR \        ( MEM_LCD_CONTROLLER_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_LOCALBUS_USER_ADDR \        ( MEM_LOCALBUS_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_LOCAL_BUS_MMU_USER_ADDR \        ( MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_HSAB_INTERFACE_USER_ADDR \        ( MEM_HSAB_INTERFACE_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_HSAB_MMU_USER_ADDR \        ( MEM_HSAB_MMU_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_TIMER_1_USER_ADDR \        ( MEM_TIMER_1_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_TIMER_2_USER_ADDR \        ( MEM_TIMER_2_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_TIMER_3_USER_ADDR \        ( MEM_TIMER_3_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_WATCH_DOG_TIMER_USER_ADDR \        ( MEM_WATCH_DOG_TIMER_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_API_INTERFACE_USER_ADDR \        ( MEM_API_INTERFACE_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_RHEA_BRIDGE_USER_ADDR \        ( MEM_RHEA_BRIDGE_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_INTH_USER_ADDR \        ( MEM_INTH_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )#define MEM_MEMORY_INTERFACE_USER_ADDR \        ( MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )/* Reserved */#define MEM_CLKM_USER_ADDR \        ( MEM_CLKM_SUPERVISOR_ADDR + MEM_USER_MODE_OFFSET )
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mem.h~ - 源码说明

本页面展示了「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器」中的 mem.h~ 源码文件，采用 H~ 编程语言编写，共 735 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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