mem.h~

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/*
===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//   Filename       	: MEM.h
//
//   Description    	: Header file for the ARM memory space mapping
//
//   Project        	: OMAP3
//
//   Author         	: Francois Reygagne [e-mail]
===============================================================================
*/
#ifndef _MEM__HH
#define _MEM__HH
 
// In the aim to make a single test
// we defined the following constants
// previously defined in the main of all 
// tests.

#include "mapping.h"

#define SVC_STK_SIZE 0x50
#define FIQ_STK_SIZE 0x50
#define IRQ_STK_SIZE 0x50
#define ABORT_STK_SIZE 0x50 

 
//----------------------------------------------------------------
//Address of Chip Select 0 To 6 dedicated to Memory Interface    -
//----------------------------------------------------------------

#define MEM_MIF_CS0_ADDRESS              0x00000000
#define MEM_MIF_CS0_LENGTH               0x02000000

#define MEM_MIF_CS1_ADDRESS              0x04000000
#define MEM_MIF_CS1_LENGTH               0x02000000

#define MEM_MIF_CS2_ADDRESS              0x08000000
#define MEM_MIF_CS2_LENGTH               0x02000000

#define MEM_MIF_CS3_ADDRESS              0x0C000000
#define MEM_MIF_CS3_LENGTH               0x02000000

#define MEM_MIF_CS4_ADDRESS              0x10000000
#define MEM_MIF_CS4_LENGTH               0x0C000000

#define MEM_MIF_CS6_ADDRESS              0x20000000
#define MEM_MIF_CS6_LENGTH               0x00032000

//=====================================================
//                debug config
//====================CS0==============================
#define  DBG_CS0_ROM_1_ADDRESS            0x00000000
#define  DBG_CS0_ROM_1_LENGTH             0x00010000

#define  DBG_CS0_RAM_2_ADDRESS            0x00010000
#define  DBG_CS0_RAM_2_LENGTH             0x00010000

#define  DBG_CS0_RAM_5_ADDRESS            0x00040000
#define  DBG_CS0_RAM_5_LENGTH             0x00040000

#define  DBG_CS0_RAM_3_ADDRESS            0x01FE0000
#define  DBG_CS0_RAM_3_LENGTH             0x00010000

#define  DBG_CS0_ROM_4_ADDRESS            0x01FF0000
#define  DBG_CS0_ROM_4_LENGTH             0x00010000
//====================CS1==============================
#define  DBG_CS1_RAM_1_ADDRESS            0x04000000
#define  DBG_CS1_RAM_1_LENGTH             0x00020000

#define  DBG_CS1_SPY_2_ADDRESS            0x05000000
#define  DBG_CS1_SPY_2_LENGTH             0x00000100

#define  DBG_CS1_STUB_3_ADDRESS           0x05000100
#define  DBG_CS1_STUB_3_LENGTH            0x05000000

#define  DBG_TB_REGS_ADDRESS              0x05000100
#define  DBG_TB_REGS_LENGTH               0x00000100

#define  DBG_CS1_RAM_4_ADDRESS            0x05FE0000
#define  DBG_CS1_RAM_4_LENGTH             0x00010000
//====================CS2==============================
#define  DBG_CS2_RAM_1_ADDRESS            0x08000000
#define  DBG_CS2_RAM_1_LENGTH             0x00020000

#define  DBG_CS2_RAM_2_ADDRESS            0x09FE0000
#define  DBG_CS2_RAM_2_LENGTH             0x00020000
//====================CS3=============================
#define  DBG_CS3_FLASHPAIR_1_ADDRESS      0x0C000000
#define  DBG_CS3_FLASHPAIR_1_LENGTH       0x00100000

#define  DBG_CS3_FLASHPAIR_2_ADDRESS      0x0DF00000
#define  DBG_CS3_FLASHPAIR_2_LENGTH       0x00100000
//====================CS4=============================
#define  DBG_CS4_SDRAM_1_ADDRESS          0x10000000
#define  DBG_CS4_SDRAM_1_LENGTH           0x00800000
//====================CS6=============================
#define  DBG_CS6_MKRAM_1_ADDRESS          0x20000000
#define  DBG_CS6_MKRAM_1_LENGTH           0x00004000




//=====================================================
//                test config
//====================CS0==============================
#define  TST_CS0_FLASH_1_ADDRESS          0x00000000
#define  TST_CS0_FLASH_1_LENGTH           0x00100000

#define  TST_CS0_FLASH_2_ADDRESS          0x01F00000
#define  TST_CS0_FLASH_2_LENGTH           0x00100000
//====================CS1==============================
#define  TST_CS1_FLASH_1_ADDRESS          0x04000000
#define  TST_CS1_FLASH_1_LENGTH           0x00100000

#define  TST_CS1_FLASH_2_ADDRESS          0x05F00000
#define  TST_CS1_FLASH_2_LENGTH           0x05FFFFFF
//====================CS2==============================
#define  TST_CS2_SRAM_1_ADDRESS           0x08000000
#define  TST_CS2_SRAM_1_LENGTH            0x00020000

#define  TST_CS2_SRAM_2_ADDRESS           0x09FE0000
#define  TST_CS2_SRAM_2_LENGTH            0x00020000
//====================CS3=============================
#define  TST_CS3_ROM_1_ADDRESS            0x0C000000
#define  TST_CS3_ROM_1_LENGTH             0x00010000

#define  TST_CS3_SPY_2_ADDRESS            0x0D000000
#define  TST_CS3_SPY_2_LENGTH             0x00000100
//====================CS4=============================
#define  TST_CS4_SDRAM_1_ADDRESS          0x10000000
#define  TST_CS4_SDRAM_1_LENGTH           0x04000000

//====================CS6=============================
#define  TST_CS6_MKRAM_1_ADDRESS          0x10000000
#define  TST_CS6_MKRAM_1_LENGTH           0x00004000



//=====================================================
//                Board config
//====================CS0==============================
// 2 devices of 16 Mbytes (INTEL STRATA E28F160J3A)
#define  BRD_CS0_FLASH_STRATA_0_ADDRESS          0x00000000
#define  BRD_CS0_FLASH_STRATA_0_LENGTH           0x01000000
#define  BRD_CS0_FLASH_STRATA_1_ADDRESS          0x01000000
#define  BRD_CS0_FLASH_STRATA_1_LENGTH           0x01000000

// or 4 devices of 2 Mbytes (INTEL BURST 28F160F3-90)
#define  BRD_CS0_FLASH_BURST_0_ADDRESS          0x00000000
#define  BRD_CS0_FLASH_BURST_0_LENGTH           0x00200000
#define  BRD_CS0_FLASH_BURST_1_ADDRESS          0x00200000
#define  BRD_CS0_FLASH_BURST_1_LENGTH           0x00200000
#define  BRD_CS0_FLASH_BURST_2_ADDRESS          0x00400000
#define  BRD_CS0_FLASH_BURST_2_LENGTH           0x00200000
#define  BRD_CS0_FLASH_BURST_3_ADDRESS          0x00600000
#define  BRD_CS0_FLASH_BURST_3_LENGTH           0x00200000

//====================CS1==============================
#define  BRD_CS1_ADDRESS          MEM_MIF_CS1_ADDRESS
#define  BRD_CS1_LENGTH 			 0
//====================CS2==============================
#define  BRD_CS2_ADDRESS          MEM_MIF_CS2_ADDRESS
#define  BRD_CS2_LENGTH 			 0
//====================CS3=============================
#define  BRD_CS3_SRAM_ADDRESS            	0x0C000000
#define  BRD_CS3_SRAM_LENGTH             	0x00080000
// 1 devices of 2 Mbytes (AMD 20LV160B )
#define  BRD_CS3_FLASH_AMD_ADDRESS   	  	0x0C080000
#define  BRD_CS3_FLASH_AMD_LENGTH        	0x00200000
//====================CS4=============================
// for MICROM MT48LC8M8A2TG, 2 devices of 8 bits data length in // (8 MBbytes)
// for NEC uPD4564163G5, 1 device of 16 bits 8 bits data length  (8 MBbytes)
#define  BRD_CS4_SDRAM_ADDRESS   	 		0x10000000
#define  BRD_CS4_SDRAM_1_LENGTH           0x0800000

// SDRAM is shared in the following sections 

// Data used for SHARED_DATA ( 1 M bytes)
#define  BRD_CS4_SDRAM_SHARED_DATA_ADDRESS  0x10000000
#define  BRD_CS4_SDRAM_SHARED_DATA_LENGTH	  0x00100000

// Data used for ARM9 stack (8 K bytes)
#define  BRD_CS4_SDRAM_ARM9_STACK_ADDRESS   0x10100000
#define  BRD_CS4_SDRAM_ARM9_STACK_LENGTH	  0x00002000

// Data used for ARM9 TTB (16 K bytes)
#define  BRD_CS4_SDRAM_TTB_ADDRESS   			0x10110000
#define  BRD_CS4_SDRAM_TTB_LENGTH	  			0x00004000

// Data used for SPY ARM9 (256 bytes)
#define  BRD_CS4_SDRAM_ARM9_SPY_ADDRESS   0x10120000
#define  BRD_CS4_SDRAM_ARM9_SPY_LENGTH	   0x00000100

// Data used for SPY GSM (256 bytes)
#define  BRD_CS4_SDRAM_GSM_SPY_ADDRESS    0x10140000
#define  BRD_CS4_SDRAM_GSM_SPY_LENGTH	   0x00000100

// Data used for GSM RANDOM DATA (128 K bytes)
#define  BRD_CS4_SDRAM_GSM_RANDOM_DATA_ADDRESS    0x10160000
#define  BRD_CS4_SDRAM_GSM_RANDOM_DATA_LENGTH	  0x00020000


// Data used for MCBSP ( 4 M bytes)
#define  BRD_CS4_SDRAM_MCBSP_DATA_ADDRESS    0x10200000
#define  BRD_CS4_SDRAM_MCBSP_DATA_LENGTH	   0x00400000

// Data used for GSM S/W (2 M bytes)
#define  BRD_CS4_SDRAM_GSM_SW_DATA_ADDRESS    0x10600000
#define  BRD_CS4_SDRAM_GSM_SW_DATA_LENGTH	    0x00200000

//====================CS6=============================
#define  BRD_CS6_MKRAM_1_ADDRESS          0x20000000
#define  BRD_CS6_MKRAM_1_LENGTH           0x00004000


/*-------------------------------------------------------------------------*/
/* PRIVATE ARM RHEA BRIDGE MAPPING                                         */
/*-------------------------------------------------------------------------*/
#define MEM_RHEA_STROBE0_ADDR	 0xfffd0000  /* Strobe 0 : address */
#define MEM_RHEA_STROBE1_ADDR	 0xfffe0000  /* Strobe 1 : address */
#define MEM_RHEA_STROBE0_NUMBER_OF_CS 32     /* Number of Chip Select per strobe */
#define MEM_RHEA_STROBE1_NUMBER_OF_CS 24     /* Number of Chip Select per strobe */
#define MEM_RHEA_STROBE_LENGTH	     2048    /* Length of a CS space 2K bytes */

/*----------------------------------------------------------------------------------*/
/* Address of strobe0 Chip Select 0 to 31                                           */
/*----------------------------------------------------------------------------------*/
#define MEM_RHEA_STROBE0_CS0_ADDR   MEM_RHEA_STROBE0_ADDR 
 
#define MEM_RHEA_STROBE0_CS1_ADDR   \
        ( MEM_RHEA_STROBE0_CS0_ADDR +      MEM_RHEA_STROBE_LENGTH )

#define MEM_RHEA_STROBE0_CS2_ADDR   \
        ( MEM_RHEA_STROBE0_CS0_ADDR + 2  * MEM_RHEA_STROBE_LENGTH )