lnk16_led.cmd

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/******************************************************************************
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments  
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product  is  protected  under  copyright  law  and  trade  secret law 
   as an unpublished work.  

   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
                                                           
   Filename       	: lnk16_led.cmd

   Description    	: Link command file for the ARM software 
   
   Project        	: ARM925ST

   Author         	: Sebastien Sabatier

   Version number	: 1.0

   Modified on 06/30/00 by [e-mail] :
      Update for Helen memory mapping.
      ARM9 boots by default on CS3, so CS3 overlay CS0 at reset.
   Modified on 08/09/01 by [e-mail] :
      Update for LED flow, add of ARM_P and LEAD_P sections 

  

  *******************************************************************************/
-f 0
-c                                         /* LINK USING C CONVENTIONS      */
-stack  0x1000                             /* SOFTWARE STACK SIZE           */
-heap   0x1000                             /* HEAP AREA SIZE                */

/* SPECIFY THE SYSTEM MEMORY MAP */

MEMORY
{
    /*-----------------------------------------------------------------------*/
    /*  NCS0:  EXTERNAL SLOW                                                 */
    /*         Intel Strataflash (32 Mbytes) or Intel Burst Flash (8 MBytes) */
    /*-----------------------------------------------------------------------*/
    /* As ARM9 boots by default on CS3 (overlay mode is set by default), CS0 */
    /* is overlayed by CS3. That why sections are defined under NCS3 part.   */
    /* If the ARM9 boots on CS0 or if the ARM9 switch to non overlay mode    */
    /* then the CS0 mapping is the following :                               */
    /*                                                                       */
    /* 0x00000000 : 0x01FFFFFF : Intel Strataflash (32 Mbytes)               */
    /* or                                                                    */
    /* 0x00000000 : 0x007FFFFF : Intel Burstflash (8 Mbytes)                 */
    /* depending on the test bench configuration.                            */
    /* In anycase, if the ARM9 code is loaded in CS0 (overlay mode disable)  */
    /* the ARM9 code will be linked with the NCS3 mapping but loaded in one  */
    /* of the 2 memory defined above.                                        */
    /*-----------------------------------------------------------------------*/


    /*-----------------------------------------------------------------------*/
    /*  NCS1:  EXTERNAL SLOW                                                 */
    /*  NCS1:  SRAM (256 kBytes)                                             */
    /*            use a ROM memory model in simulation                       */
    /*         SPY area (256 bytes)                                          */
    /*         Test Bench Registers area (256 bytes)                         */
    /*-----------------------------------------------------------------------*/
    NCS1_MEM1: org = 0x04000000   len = 0x00040000  /* 256 K-Bytes */

    SPY_RES:   org = 0x05000000	  len = 0x100       /* 256 bytes */  
    STUB:      org = 0x05000100	  len = 0x100       /* 256 bytes */  


    /*-----------------------------------------------------------------------*/
    /*  NCS2:  EXTERNAL SLOW                                                 */
    /*  Not used in RTL simulation, no memory mapped on this CS              */
    /*-----------------------------------------------------------------------*/


    /*-----------------------------------------------------------------------*/
    /*  NCS3: EXTERNAL SLOW                                                  */
    /*        SRAM (256 kBytes)                                              */
    /*            use a ROM memory model in simulation                       */
    /*        AMD Sectored Flash (1 MBytes)                                  */
    /*-----------------------------------------------------------------------*/
    /* If the ARM9 boots on CS0 or if the ARM9 switches to non overlay mode  */
    /* the the CS3 mapping is the following :                                */
    /*                                                                       */
    /* 0x0C000000 : 0x0003FFFF : SRAM (256 Kbytes)                           */
    /* 0x0C040000 : 0x0C13FFFF : AMD Sectored Flash (1 Mbytes)               */
    /*-----------------------------------------------------------------------*/
    I_MEM    : org = 0x00000000   len = 0x00000020  /* INTERRUPTS               */
    
    ARM_P  : org = 0x00000020   len = 0x000FFE0  /* PROGRAM MEMORY (ROM) */
    LEAD_P : org = 0x00010000   len = 0x00010000  /* PROGRAM MEMORY (ROM) */

    
    SPY_RES2:  org = 0x0D000000   len = 0x100       /* 256 bytes */
    STUB2:     org = 0x0D000100   len = 0x100       /* 256 bytes */

    /*-----------------------------------------------------------------------*/
    /*  NCS4: EXTERNAL FAST                                                  */
    /*        NEC SDRAM (8 MBytes) or MICRON SDRAM (8 MBytes)                */  
    /*-----------------------------------------------------------------------*/
    NCS4_MEM1: org = 0x10000000   len = 0x00800000   /* 8M-Bytes DATA MEMORY */


    /*-----------------------------------------------------------------------*/
    /*  NCS6: INTERNAL MKRAM  DATA                                           */
    /*        16 Kbytes 8/16/32 R/W                                          */
    /*-----------------------------------------------------------------------*/ 
     S_MEM:    org = 0x20000000   len = 0x03F00  
 
    /*-----------------------------------------------------------------------*/
    /*  ARM RHEA BRIDGE ADDRESS MAPPING                                      */
    /*-----------------------------------------------------------------------*/
    RHEA_STROBE0_CS0_ADDR : org = 0xfffd0000  len = 0x800 

    RHEA_STROBE1_CS0_ADDR : org = 0xfffe0000  len = 0x800 

}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */

SECTIONS
{
    .intvecs : {} > I_MEM        /* INTERRUPT VECTORS                 */
    .bss     : {} > S_MEM        /* GLOBAL & STATIC VARS              */
    .sysmem  : {} > S_MEM        /* DYNAMIC MEMORY ALLOCATION AREA    */
    .stack   : {} > S_MEM        /* SOFTWARE SYSTEM STACK             */
    .data    : {} > S_MEM        /* RAM data (used by ASM)            */

    .exitsim : {} > ARM_P        /* CODE                              */
    .text    : {} > ARM_P        /* CODE                              */
    .f16st   : {} > ARM_P
    .f16end  : {} > ARM_P
    .f32st   : {} > ARM_P 
    .f32end  : {} > ARM_P
    .cinit   : {} > ARM_P        /* INITIALIZATION TABLES */
    .const   : {} > ARM_P        /* CONSTANT DATA */

    loadprog    : {} > LEAD_P        /* CODE                              */
    loadint     : {} > LEAD_P        /* CODE                              */
    daram0        : {} > LEAD_P        /* CODE                              */
    daram1        : {} > LEAD_P        /* CODE                              */

    .spy     : {} > SPY_RES      /* spy result area*/
    .spytest : {} > SPY_RES2     /* spy result area*/
   
   
}