emiff_emifs_wt.h

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/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 2000, (C) Copyright 2001 Texas Instruments.  All rights reserved.

   Filename       	: EMIFF_EMIFS_WT.h

   Description    	: Header file for the EMIFF, EMIFS and WT module

   Project        	: OMAP3.2

   Author         	: Pradosh K. Puthanpurayil

   Date			: 11/14/2001

 FUNCTIONS PROVIDED   	:

===============================================================================
*/

#ifndef _EMIFF_EMIFS_WT_HH
#define _EMIFF_EMIFS_WT_HH

#include "top.h"


//-----------------------------------------------------------------------------
//-- REGISTERS MAPPING ADDRESS                                                -
//-----------------------------------------------------------------------------

//-- EXTERNAL MEMORY INTERFACE FAST (EMIFF) REGISTERS

#define EMIFF_REGISTER_BASE_ADDR		0xFFFECC00

#define EMIFF_PRIORITY_REG			(EMIFF_REGISTER_BASE_ADDR + 0x08)
#define EMIFF_CONFIG_REG			(EMIFF_REGISTER_BASE_ADDR + 0x20)
#define EMIFF_MRS_REG				(EMIFF_REGISTER_BASE_ADDR + 0x24)
#define EMIFF_CONFIG2_REG			(EMIFF_REGISTER_BASE_ADDR + 0x3C)
#define EMIFF_MRS_NEW_REG			(EMIFF_REGISTER_BASE_ADDR + 0x70)
#define EMIFF_EMRS1_REG				(EMIFF_REGISTER_BASE_ADDR + 0x74)
//#define EMIFF_EMRS2_REG			(EMIFF_REGISTER_BASE_ADDR + 0x78)
#define EMIFF_EMRS2_REG			    (EMIFF_REGISTER_BASE_ADDR + 0x78)
#define EMIFF_EMRS2_REG				(EMIFF_REGISTER_BASE_ADDR + 0x78)
#define EMIFF_EMRS3_REG				(EMIFF_REGISTER_BASE_ADDR + 0xC8)
#define EMIFF_OPERATION_REG			(EMIFF_REGISTER_BASE_ADDR + 0x80)
#define EMIFF_MANUAL_CMD_REG			(EMIFF_REGISTER_BASE_ADDR + 0x84)
#define EMIFF_DYN_PRI_TIMEOUT1_REG		(EMIFF_REGISTER_BASE_ADDR + 0x8C)
#define EMIFF_DYN_PRI_TIMEOUT2_REG		(EMIFF_REGISTER_BASE_ADDR + 0x90)
#define EMIFF_DYN_PRI_TIMEOUT3_REG		(EMIFF_REGISTER_BASE_ADDR + 0x94)
#define EMIFF_ABORT_REG				(EMIFF_REGISTER_BASE_ADDR + 0x98)
#define EMIFF_ABORT_TYPE_REG			(EMIFF_REGISTER_BASE_ADDR + 0x9C)
#define EMIFF_DLL_URD_CTRL_REG			(EMIFF_REGISTER_BASE_ADDR + 0xC0)
#define EMIFF_DLL_URD_STATUS_REG		(EMIFF_REGISTER_BASE_ADDR + 0xC4)
#define EMIFF_DLL_LRD_CTRL_REG			(EMIFF_REGISTER_BASE_ADDR + 0xCC)
#define EMIFF_DLL_LRD_STATUS_REG		(EMIFF_REGISTER_BASE_ADDR + 0xBC)
#define EMIFF_DLL_WRT_CTRL_REG			(EMIFF_REGISTER_BASE_ADDR + 0x64)
#define EMIFF_DLL_WRT_STATUS_REG		(EMIFF_REGISTER_BASE_ADDR + 0x68)


//-- EXTERNAL MEMORY INTERFACE SLOW (EMIFS) REGISTERS

#define EMIFS_REGISTER_BASE_ADDR		0xFFFECC00

#define EMIFS_PRIORITY_REG			(EMIFS_REGISTER_BASE_ADDR + 0x04)
#define EMIFS_CONFIG_REG			(EMIFS_REGISTER_BASE_ADDR + 0x0C)
#define EMIFS_nCS0_CONFIG_REG			(EMIFS_REGISTER_BASE_ADDR + 0x10)
#define EMIFS_nCS1_CONFIG_REG			(EMIFS_REGISTER_BASE_ADDR + 0x14)
#define EMIFS_nCS2_CONFIG_REG			(EMIFS_REGISTER_BASE_ADDR + 0x18)
#define EMIFS_nCS3_CONFIG_REG			(EMIFS_REGISTER_BASE_ADDR + 0x1C)
#define EMIFS_DYN_WAIT_STATE_REG		(EMIFS_REGISTER_BASE_ADDR + 0x40)
#define EMIFS_DYN_PRI_TIMEOUT1_REG		(EMIFS_REGISTER_BASE_ADDR + 0x28)
#define EMIFS_DYN_PRI_TIMEOUT2_REG		(EMIFS_REGISTER_BASE_ADDR + 0x2C)
#define EMIFS_DYN_PRI_TIMEOUT3_REG		(EMIFS_REGISTER_BASE_ADDR + 0x30)
#define EMIFS_ABORT_ADDRESS_REG			(EMIFS_REGISTER_BASE_ADDR + 0x44)
#define EMIFS_ABORT_TYPE_REG			(EMIFS_REGISTER_BASE_ADDR + 0x48)
#define EMIFS_ABORT_TIMEOUT_REG			(EMIFS_REGISTER_BASE_ADDR + 0x4C)
//New registers added as per ECN1 change
#define EMIFS_ADV_nCS0_CONFIG_REG		(EMIFS_REGISTER_BASE_ADDR + 0x50)
#define EMIFS_ADV_nCS1_CONFIG_REG		(EMIFS_REGISTER_BASE_ADDR + 0x54)
#define EMIFS_ADV_nCS2_CONFIG_REG		(EMIFS_REGISTER_BASE_ADDR + 0x58)
#define EMIFS_ADV_nCS3_CONFIG_REG		(EMIFS_REGISTER_BASE_ADDR + 0x5C)


//-- WINDOW TRACER (WT) REGISTERS

#define WT_REGISTER_BASE_ADDR			0xFFFED500

#define WT_EMIFF_W1_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x00)
#define WT_EMIFF_W1_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x04)
#define WT_EMIFF_W2_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x08)
#define WT_EMIFF_W2_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x0C)
#define WT_EMIFS_W1_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x10)
#define WT_EMIFS_W1_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x14)
#define WT_EMIFS_W2_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x18)
#define WT_EMIFS_W2_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x1C)
#define WT_OCPT1_W1_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x20)
#define WT_OCPT1_W1_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x24)
#define WT_OCPT1_W2_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x28)
#define WT_OCPT1_W2_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x2C)
#define WT_OCPT2_W1_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x30)
#define WT_OCPT2_W1_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x34)
#define WT_OCPT2_W2_TOPADDR_REG			(WT_REGISTER_BASE_ADDR + 0x38)
#define WT_OCPT2_W2_BOTADDR_REG			(WT_REGISTER_BASE_ADDR + 0x3C)
#define WT_WIN_ENABLE_REG			(WT_REGISTER_BASE_ADDR + 0x40)


//-----------------------------------------------------------------------------
//-- REGISTERS RESET VALUE                                                    -
//-----------------------------------------------------------------------------

//-- EXTERNAL MEMORY INTERFACE FAST (EMIFF) REGISTERS

#define EMIFF_PRI_RESET_VALUE			0x00000000
#define EMIFF_CONFIG_RESET_VALUE		0x00618802
#define EMIFF_MRS_RESET_VALUE			0x00000037
#define EMIFF_CONFIG2_RESET_VALUE		0x00000003
#define EMIFF_MRS_NEW_RESET_VALUE		0x00000037
#define EMIFF_EMRS1_RESET_VALUE			0x00000000
#define EMIFF_EMRS2_RESET_VALUE			0x00000000
#define EMIFF_EMRS3_RESET_VALUE			0x00000000
#define EMIFF_OPERATION_RESET_VALUE		0x00000004
#define EMIFF_MANUAL_CMD_RESET_VALUE		0x00000000
#define EMIFF_DYN_PRI_TO1_RESET_VALUE		0x00000000
#define EMIFF_DYN_PRI_TO2_RESET_VALUE		0x00000000
#define EMIFF_DYN_PRI_TO3_RESET_VALUE		0x00000000
#define EMIFF_ABORT_RESET_VALUE			0x10000000
#define EMIFF_ABORT_TYPE_RESET_VALUE		0x00000000
#define EMIFF_DLL_URD_CTRL_RESET_VALUE		0x00000000
#define EMIFF_DLL_URD_STATUS_RESET_VALUE	0x00000000
#define EMIFF_DLL_LRD_CTRL_RESET_VALUE		0x00000000
#define EMIFF_DLL_LRD_STATUS_RESET_VALUE	0x00000000
#define EMIFF_DLL_WRT_CTRL_RESET_VALUE		0x00000000
#define EMIFF_DLL_WRT_STATUS_RESET_VALUE	0x00000000


//-- EXTERNAL MEMORY INTERFACE FAST (EMIFS) REGISTERS

#define EMIFS_PRI_RESET_VALUE			0x00000000

//#define EMIFS_CONFIG_RESET_VALUE		0x00001FF9
#define EMIFS_CONFIG_RESET_VALUE		0x00000000

#define EMIFS_nCS0_CONFIG_RESET_VALUE		0x0010FFFB

#define EMIFS_nCS1_CONFIG_RESET_VALUE		0x0010FFFB

#define EMIFS_nCS2_CONFIG_RESET_VALUE		0x0010FFFB

#define EMIFS_nCS3_CONFIG_RESET_VALUE		0x0010FFFB

#define EMIFS_DYN_WAIT_ST_RESET_VALUE		0x00000000
#define EMIFS_DYN_PRI_TO1_RESET_VALUE		0x00000000
#define EMIFS_DYN_PRI_TO2_RESET_VALUE		0x00000000
#define EMIFS_DYN_PRI_TO3_RESET_VALUE		0x00000000
#define EMIFS_ABORT_ADDR_RESET_VALUE		0x00000000
#define EMIFS_ABORT_TYPE_RESET_VALUE		0x00000000
#define EMIFS_ABORT_TO_RESET_VALUE		0x000001FF
//New registers (ECN1)
#define EMIFS_ADV_nCS0_RESET_VALUE		0x00000000
#define EMIFS_ADV_nCS1_RESET_VALUE		0x00000000
#define EMIFS_ADV_nCS2_RESET_VALUE		0x00000000
#define EMIFS_ADV_nCS3_RESET_VALUE		0x00000000


//-- WINDOW TRACER (WT) REGISTERS

#define WT_EMIFF_W1_TOPADDR_RESET_VALUE		0x00000000
#define WT_EMIFF_W1_BOTADDR_RESET_VALUE		0x00000000
#define WT_EMIFF_W2_TOPADDR_RESET_VALUE		0x00000000
#define WT_EMIFF_W2_BOTADDR_RESET_VALUE		0x00000000	
#define WT_EMIFS_W1_TOPADDR_RESET_VALUE		0x00000000	
#define WT_EMIFS_W1_BOTADDR_RESET_VALUE		0x00000000	
#define WT_EMIFS_W2_TOPADDR_RESET_VALUE		0x00000000	
#define WT_EMIFS_W2_BOTADDR_RESET_VALUE		0x00000000	
#define WT_OCPT1_W1_TOPADDR_RESET_VALUE		0x00000000	
#define WT_OCPT1_W1_BOTADDR_RESET_VALUE		0x00000000	
#define WT_OCPT1_W2_TOPADDR_RESET_VALUE		0x00000000	
#define WT_OCPT1_W2_BOTADDR_RESET_VALUE		0x00000000	
#define WT_OCPT2_W1_TOPADDR_RESET_VALUE		0x00000000	
#define WT_OCPT2_W1_BOTADDR_RESET_VALUE		0x00000000	
#define WT_OCPT2_W2_TOPADDR_RESET_VALUE		0x00000000	
#define WT_OCPT2_W2_BOTADDR_RESET_VALUE		0x00000000	
#define WT_WIN_ENABLE_RESET_VALUE		0x00000000	


//-----------------------------------------------------------------------------
//-- REGISTERS READ WRITE BITS AND READ ONLY BITS MASK VALUE                                                    -
//-----------------------------------------------------------------------------

//-- EMIF FAST REGISTERS
#define EMIFF_PRI_RW_MSK			0x0000FF77

#define EMIFF_CONFIG_RW_MSK			0x3FFFFFFD

#define EMIFF_MRS_RW_MSK			0x0000027F

#define EMIFF_CONFIG2_RW_MSK			0x00000003

#define EMIFF_MRS_NEW_RW_MSK			0x0000027F

#define EMIFF_EMRS1_RW_MSK			0x00000007

#define EMIFF_EMRS2_RW_MSK			0x0000001F

#define EMIFF_OPERATION_RW_MSK			0xFFFFFFFF

#define EMIFF_MANUAL_CMD_RW_MSK			0x0000000F

#define EMIFF_DYN_PRI_TO1_RW_MSK		0x000000FF

#define EMIFF_DYN_PRI_TO2_RW_MSK		0x00FF00FF

#define EMIFF_DYN_PRI_TO3_RW_MSK		0x000000FF

#define EMIFF_DLL_CTRL_RW_MSK			0xFFF0FF0E

#define EMIFF_DLL_STATUS_RW_MSK			0x0000FF07

#define EMIFF_ABORT_READ_ONLY_MSK		0x1FFFFFFF

#define EMIFF_ABORT_TYPE_READ_ONLY_MSK		0x0000001F

#define EMIFF_ABORT_TYPE_RW_MSK			0x00000007

#define EMIFF_DLL_URD_CTRL_RW_MSK		0x03F0FF0E

#define EMIFF_DLL_URD_STATUS_RD_MSK		0x0000FF07

#define EMIFF_DLL_LRD_CTRL_RW_MSK		0x03F0FF0E

#define EMIFF_DLL_LRD_STATUS_RD_MSK		0x0000FF07

#define EMIFF_DLL_WRT_CTRL_RW_MSK		0x03F0FF0E

#define EMIFF_DLL_WRT_STATUS_RD_MSK		0x0000FF07


//-- EMIFS REGISTERS
#define EMIFS_PRI_RW_MSK			0x0000FF77

#define EMIFS_CONFIG_RW_MSK			0x0000000F
#define EMIFS_CONFIG_READ_ONLY_MSK		0x00000010

//Change in RW mask as per ECN1
//#define EMIFS_nCS0_CONFIG_RW_MSK		0x07F7FFF7 //Old
#define EMIFS_nCS0_CONFIG_RW_MSK		0xFFF7FFF7
#define EMIFS_nCS1_CONFIG_RW_MSK		0xFFF7FFF7
#define EMIFS_nCS2_CONFIG_RW_MSK		0xFFF7FFF7
#define EMIFS_nCS3_CONFIG_RW_MSK		0xFFF7FFF7

//ECN1 change
#define EMIFS_DYN_WAIT_ST_RW_MSK		0x000000FF

#define EMIFS_DYN_PRI_TO1_RW_MSK		0x000000FF
#define EMIFS_DYN_PRI_TO2_RW_MSK		0x000000FF
#define EMIFS_DYN_PRI_TO3_RW_MSK		0x000000FF
#define EMIFS_ABORT_ADDR_READ_ONLY_MSK		0xFFFFFFFF
#define EMIFS_ABORT_TYPE_READ_ONLY_MSK		0x0000001F
#define EMIFS_ABORT_TO_RW_MSK			0x000001FF
//New Registers
#define EMIFS_ADV_nCS0_CONFIG_RW_MSK		0x000001FF
#define EMIFS_ADV_nCS1_CONFIG_RW_MSK		0x000001FF
#define EMIFS_ADV_nCS2_CONFIG_RW_MSK		0x000001FF
#define EMIFS_ADV_nCS3_CONFIG_RW_MSK		0x000001FF
 
 
 
//-- WINDOW TRACER (WT) REGISTERS
#define WT_EMIFF_W1_TOPADDR_RW_MSK		0x0FFFFFFF
#define WT_EMIFF_W1_BOTADDR_RW_MSK		0x0FFFFFFF
#define WT_EMIFF_W2_TOPADDR_RW_MSK		0x0FFFFFFF
#define WT_EMIFF_W2_BOTADDR_RW_MSK		0x0FFFFFFF	
#define WT_EMIFS_W1_TOPADDR_RW_MSK		0x0FFFFFFF	
#define WT_EMIFS_W1_BOTADDR_RW_MSK		0x0FFFFFFF	
#define WT_EMIFS_W2_TOPADDR_RW_MSK		0x0FFFFFFF	
#define WT_EMIFS_W2_BOTADDR_RW_MSK		0x0FFFFFFF	
#define WT_OCPT1_W1_TOPADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT1_W1_BOTADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT1_W2_TOPADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT1_W2_BOTADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT2_W1_TOPADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT2_W1_BOTADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT2_W2_TOPADDR_RW_MSK		0xFFFFFFFF	
#define WT_OCPT2_W2_BOTADDR_RW_MSK		0xFFFFFFFF	
#define WT_WIN_ENABLE_RW_MSK			0x000000FF	

//-----------------------------------------------------------------------------
//-- EMIFF REGISTER FIELD MASKS AND BIT POSITION                                    -
//-----------------------------------------------------------------------------

//-- EMIFF PRIORITY REGISTER
#define EMIFF_ARM_PRIORITY_MSK		0x00000007 /* ARM Consecutive Access Mask */
#define EMIFF_DSP_PRIORITY_MSK		0x00000070 /* DSP Consecutive Access Mask */
#define EMIFF_DMA_PRIORITY_MSK		0x00000F00 /* DMA Consecutive Access Mask */
#define EMIFF_OCPI_PRIORITY_MSK		0x0000F000 /* OCPI Consecutive Access Mask */

#define EMIFF_ARM_PRIORITY_BITPOS	0  
#define EMIFF_DSP_PRIORITY_BITPOS   	4
#define EMIFF_DMA_PRIORITY_BITPOS   	8
#define EMIFF_OCPI_PRIORITY_BITPOS 	12
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emiff_emifs_wt.h - 源码说明

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