fpga.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION

   Property of Texas Instruments
   For  Unrestricted  Internal  Use  Only
   Unauthorized reproduction and/or distribution is strictly prohibited.
   This product is protected under copyright law and trade secret law
   as an unpublished work.
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : fpga.h

   Description          : OMAP1510TEB fpga

   Project              : Helen1

===============================================================================
*/
#ifndef _FPGA__HH
#define _FPGA__HH

#include "global_types.h"

//for OMAP1510TEB
#ifdef APEX




// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Base address of FPGA integrated circuit
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define FPGA_ADDR	0x08000000

//
// ~~~~~~~~~~~~
//    OFFSET
// ~~~~~~~~~~~~
#define FPGA_ELPD_REVISION_REG_OFFSET		0x0
#define FPGA_FP_LED_LCD_REG_OFFSET			0x2
#define FPGA_FRONT_PANEL_LED_OFFSET			0x3
#define FPGA_POWER_REG_OFFSET					0x4
#define FPGA_IT_STATUS_REG_OFFSET			0x6
#define FPGA_IT_MASK_REG_OFFSET				0x8
#define FPGA_PERIPH_RESET_REG_OFFSET		0xB
#define FPGA_CTRL_REG_OFFSET					0xD
#define FPGA_IO_REG_OFFSET						0xF
//
// ~~~~~~~~~~~~
//   ADDRESS
// ~~~~~~~~~~~~
#define FPGA_ELPD_REVISION_ADDR 		(FPGA_ADDR + FPGA_ELPD_REVISION_REG_OFFSET)
#define FPGA_FP_LED_LCD_ADDR			(FPGA_ADDR + FPGA_FP_LED_LCD_REG_OFFSET)
#define FPGA_FRONT_PANEL_LED_ADDR	(FPGA_ADDR + FPGA_FRONT_PANEL_LED_OFFSET)
#define FPGA_POWER_ADDR					(FPGA_ADDR + FPGA_POWER_REG_OFFSET)
#define FPGA_IT_STATUS_ADDR			(FPGA_ADDR + FPGA_IT_STATUS_REG_OFFSET)
#define FPGA_IT_MASK_ADDR				(FPGA_ADDR + FPGA_IT_MASK_REG_OFFSET)
#define FPGA_PERIPH_RESET_ADDR		(FPGA_ADDR + FPGA_PERIPH_RESET_REG_OFFSET)
#define FPGA_CTRL_ADDR					(FPGA_ADDR + FPGA_CTRL_REG_OFFSET)
#define FPGA_IO_ADDR						(FPGA_ADDR + FPGA_IO_REG_OFFSET)

//
// ~~~~~~~~~~~~~~~~~~~~~~~
// REGISTER MASK DEFINITION
// ~~~~~~~~~~~~~~~~~~~~~~~
// LED_LCD register
#define	LED_MASK	      0xFF00
#define	BLE_MASK	      0x0001
#define	FRONT_LED_MASK	0x00FF
#define  VDD_MASK	      0x0002
#define  VEE_MASK	      0x0004

// power status register
#define SD_AUDIO_MASK		0x0100
#define USBC_PWR_MASK		0x0200
#define USBH_PWR_MASK		0x0400
#define EXTBOARD_EN_MASK	0x0800
#define CAM_EN_MASK			0x1000
#define SHDN_UART1_MASK		0x2000
#define SHDN_UART2_MASK		0x4000
#define SHDN_UART3_MASK		0x8000

// interrupt status register
#define IT_TI_MASK	0x0800
#define IT_DCD_MASK	0x1000
#define GSM_IRQ_MASK	0x2000
#define ETH_INT_MASK	0x4000
#define IT_EXT_MASK	0x8000

// interrupt mask register
#define MIT_TI_MASK	0x0800
#define MIT_DCD_MASK	0x1000
#define GSM_MIRQ_MASK	0x2000
#define ETH_MINT_MASK	0x4000
#define MIT_EXT_MASK	0x8000

// peripheral reset register
#define CAM_RESET_CMD_MASK 0x0010
#define BLUETOOTH_RST_MASK 0x0020

// Control register
#define EN_EXT_IO_0_MASK	 0x0100
#define EN_EXT_IO_1_MASK	 0x0200
#define MPU_RI_MASK			 0x0400
#define ELPD_DCD_MASK		 0x0800
#define SHDN_MPU_UART2_MASK 0x1000
#define SHDN_MPU_UART_MASK	 0x2000
#define AUDIO_AMP_PD_MASK	 0x4000





//----------------------------------------------------------------------------
// 7 Segment LED Display definition
//----------------------------------------------------------------------------
#define LED_DISPLAY_0 0x80
#define LED_DISPLAY_1 0xF2
#define LED_DISPLAY_2 0x48
#define LED_DISPLAY_3 0x60
#define LED_DISPLAY_4 0x32
#define LED_DISPLAY_5 0x24
#define LED_DISPLAY_6 0x04
#define LED_DISPLAY_7 0xF0
#define LED_DISPLAY_8 0x00
#define LED_DISPLAY_9 0x20
#define LED_DISPLAY_A 0x10
#define LED_DISPLAY_B 0x06
#define LED_DISPLAY_C 0x4E
#define LED_DISPLAY_D 0x42
#define LED_DISPLAY_E 0x0C
#define LED_DISPLAY_F 0x1C
#define LED_DISPLAY_P 0x18
#define LED_DISPLAY_C2 0x8C


void FPGA_Write(UWORD32 reg_add, UWORD16 reg_mask, UWORD16 reg_value);
UWORD16 FPGA_Read(UWORD32 reg_add);

UWORD16 FPGA_RevisionRead(void);
//-----------------------------------------------------------
// 7 Segment Display macro
//-----------------------------------------------------------
#define FPGA_DISPLAY_LED(value) \
{ \
 *(REGISTER_UWORD8*)FPGA_FRONT_PANEL_LED_ADDR = value; \
}

#else

// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Base address of FPGA integrated circuit
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define FPGA_ADDRESS	0x97FFFFE
#define FPGA_REG REG16(FPGA_ADDRESS)


// ~~~~~~~~~~~~~~~~~~~~~~~
// REGISTER MASK DEFINITION
// ~~~~~~~~~~~~~~~~~~~~~~~
#define SD_AUDIO_MSK 	0x01
#define CAM_RESET_CMD_MSK	0x02
#define NRESET_BT_OUT_MSK	0x04
#define AU_SPD_MCLK_EN_MSK	0x08
#define AU_SPD_MCLK_SEL_MSK	0x10
#define HID_RESET_MSK		0x20
#define FREQ4MHZ_CLK_EN_MSK	0x40
#define FREQ48MHZ_CLK_EN_MSK	0x80
#define SPARE1_LCD_CMD_MSK	0x100
#define SPARE8_LCD_CMD_MSK	0x200
#define IO_ENABBLK_MSK		0x400
#define IO_ENAVDD_MSK		0x800
#define IO_ENAVEE_MSK		0x1000
#define SHDN_UART_B_MSK		0x2000
#define SHDN_UART2_B_MSK	0x4000

#define DEFAULT_REGISTER_FPGA_VALUE  0x001B

void FPGA_Write(UWORD16 reg_mask, UWORD16 value);
UWORD16 FPGA_Read(void);

#endif



#endif