📄 camera.h
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//=====================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 1987,(C) Copyright 2000 Texas Instruments.
// All rights reserved.
//
// Filename : camera.h
//
// Description : Test access to all configuration registers of Helen Camera IF
//
// Project : HELEN
//
// First creation : Jean-Philippe Ulpiano (jp_ulpiano@ti.com)
//
//
//===================================================================== Update for camera cpu test
// modified for PERSEUS2.5 : Andrea Sterpin (a-sterpin@ti.com)
#ifndef _CAMERA_H
#define _CAMERA_H
#include "result.h"
#include "test.h"
#include "global_types.h"
#include "reset.h"
#define TIMEOUT_DMA_CHANNEL_0_TRANSFER 100
#define TIMEOUT_CAMIF 700
// 1- 1> Add; This is used instead of "BYTES_PER_LINE_QCIF"
#define BYTES_PER_LINE_PGtest 176
// 2- 2> Add; This is used instead of "LINES_PER_FRAME_QCIF"
#define LINES_PER_FRAME_PGtest 105
#ifdef SET32BITS
#undef SET32BITS
#endif
#define SET32BITS(ADDR) ((ADDR)<<2)
// defines for the structures of images (there is a scale factor for simu)
# define BYTES_PER_LINE_CIF 704
# define BYTES_PER_LINE_QCIF 44
# define BYTES_PER_LINE_VGA 1280
# define BYTES_PER_LINE_QVGA 20
#define LINES_PER_FRAME_CIF 4
#define LINES_PER_FRAME_QCIF 4
#define LINES_PER_FRAME_VGA 4
#define LINES_PER_FRAME_QVGA 8
//=================================================================
//
// Camera IF register !! 32 bits register !!
// ============================================
//
//
// Clock Control Register
//========================
#define CAMIF_CCR_REG_OFFSET SET32BITS(0x00)
#define CAMIF_CCR_REG (CAMIF_BASE_ADDRESS + CAMIF_CCR_REG_OFFSET )
//Mask values
#define CAMIF_CCR_FOSCMOD_MASK 0x00000007
#define CAMIF_CCR_POLCLK_MASK 0x00000008
#define CAMIF_CCR_CAMEXCLKEN_MASK 0x00000010
#define CAMIF_CCR_OCPCLKEN_MASK 0x00000020
//#define CAMIF_CCR_DPLLEN_MASK 0x00000040 //BIT 6 RESERVED
#define CAMIF_CCR_LCLKEN_MASK 0x00000080
#define CAMIF_CCR_REG_MASK 0x000001BF
//Length field
#define CAMIF_CCR_FOSCMOD_NUMB 3
#define CAMIF_CCR_POLCLK_NUMB 1
#define CAMIF_CCR_CAMEXCLKEN_NUMB 1
#define CAMIF_CCR_OCPCLKEN_NUMB 1
//#define CAMIF_CCR_DPLLEN_NUMB 1
#define CAMIF_CCR_LCLKEN_NUMB 1
//Pos values
#define CAMIF_CCR_FOSCMOD_POS 0
#define CAMIF_CCR_POLCLK_POS 3
#define CAMIF_CCR_CAMEXCLKEN_POS 4
#define CAMIF_CCR_OCPCLKEN_POS 5
//#define CAMIF_CCR_DPLLEN_POS 6
#define CAMIF_CCR_LCLKEN_POS 7
//Reset values
#define CAMIF_CCR_FOSCMOD_RES_VAL 0x0
#define CAMIF_CCR_POLCLK_RES_VAL 0x0
#define CAMIF_CCR_CAMEXCLKEN_RES_VAL 0x0
#define CAMIF_CCR_OCPCLKEN_RES_VAL 0x0
//#define CAMIF_CCR_DPLLEN_RES_VAL 0x0
#define CAMIF_CCR_LCLKEN_RES_VAL 0x0
#define CAMIF_CK_ENABLE 1
#define CAMIF_CK_DISABLE 0
// Interrupt Register
//====================
#ifdef __ES20__
#define CAMIF_IR_REG_OFFSET SET32BITS(0x4)
#else
#define CAMIF_IR_REG_OFFSET SET32BITS(0x01)
#endif
#define CAMIF_IR_REG (CAMIF_BASE_ADDRESS + CAMIF_IR_REG_OFFSET )
//Mask values
#define CAMIF_IR_VUP_MASK 0x00000001
#define CAMIF_IR_VDOWN_MASK 0x00000002
#define CAMIF_IR_HUP_MASK 0x00000004
#define CAMIF_IR_HDOWN_MASK 0x00000008
#define CAMIF_IR_FIFOFULL_MASK 0x00000010
#define CAMIF_IR_DATATRANSFER_MASK 0x00000020
#define CAMIF_IR_REG_MASK 0x0000003F
//building of CAMIF_IR_MASK (=0x0000003F)
#define CAMIF_IR_MASK \
((((2<<(CAMIF_IR_VUP_NUMB-1))-1)<<CAMIF_IR_VUP_POS)|\
(((2<<(CAMIF_IR_VDOWN_NUMB-1))-1)<<CAMIF_IR_VDOWN_POS)|\
(((2<<(CAMIF_IR_HUP_NUMB-1))-1)<<CAMIF_IR_HUP_POS)|\
(((2<<(CAMIF_IR_HDOWN_NUMB-1))-1)<<CAMIF_IR_HDOWN_POS)|\
(((2<<(CAMIF_IR_FIFOFULL_NUMB-1))-1)<<CAMIF_IR_FIFOFULL_POS)|\
(((2<<(CAMIF_IR_DATATRANSFER_NUMB-1))-1)<<CAMIF_IR_DATATRANSFER_POS))
#define CAMIF_IR_RES_VAL \
((CAMIF_IR_VUP_RES_VAL<<CAMIF_IR_VUP_POS)|\
(CAMIF_IR_VDOWN_RES_VAL<<CAMIF_IR_VDOWN_POS)|\
(CAMIF_IR_HUP_RES_VAL<<CAMIF_IR_HUP_POS)|\
(CAMIF_IR_HDOWN_RES_VAL<<CAMIF_IR_HDOWN_POS)|\
(CAMIF_IR_FIFOFULL_RES_VAL<<CAMIF_IR_FIFOFULL_POS)|\
(CAMIF_IR_DATATRANSFER_RES_VAL<<CAMIF_IR_DATATRANSFER_POS))
//Length field
#define CAMIF_IR_VUP_NUMB 1
#define CAMIF_IR_VDOWN_NUMB 1
#define CAMIF_IR_HUP_NUMB 1
#define CAMIF_IR_HDOWN_NUMB 1
#define CAMIF_IR_FIFOFULL_NUMB 1
#define CAMIF_IR_DATATRANSFER_NUMB 1
//Pos values
#define CAMIF_IR_VUP_POS 0
#define CAMIF_IR_VDOWN_POS 1
#define CAMIF_IR_HUP_POS 2
#define CAMIF_IR_HDOWN_POS 3
#define CAMIF_IR_FIFOFULL_POS 4
#define CAMIF_IR_DATATRANSFER_POS 5
//Reset values
#define CAMIF_IR_VUP_RES_VAL 0x0
#define CAMIF_IR_VDOWN_RES_VAL 0x0
#define CAMIF_IR_HUP_RES_VAL 0x0
#define CAMIF_IR_HDOWN_RES_VAL 0x0
#define CAMIF_IR_FIFOFULL_RES_VAL 0x0
#define CAMIF_IR_DATATRANSFER_RES_VAL 0x0
// Mode Register
//===============
#ifdef __ES20_
#define CAMIF_MD_REG_OFFSET SET32BITS(0x8)
#else
#define CAMIF_MD_REG_OFFSET SET32BITS(0x02)
#endif
#define CAMIF_MD_REG (CAMIF_BASE_ADDRESS + CAMIF_MD_REG_OFFSET )
//Mask values
//#define CAMIF_MD_CAMOSC_MASK 0x00000001 //BIT 0 RESERVED
//#define CAMIF_MD_IMGSIZE_MASK 0x00000006 //BITS 2:1 RESERVED
#define CAMIF_MD_ORDERCAMD_MASK 0x00000008
#define CAMIF_MD_ENVUP_MASK 0x00000010
#define CAMIF_MD_ENVDOWN_MASK 0x00000020
#define CAMIF_MD_ENHUP_MASK 0x00000040
#define CAMIF_MD_ENHDOWN_MASK 0x00000080
#define CAMIF_MD_DMA_MASK 0x00000100
#define CAMIF_MD_THRESHOLD_MASK 0x0000FE00
#define CAMIF_MD_ENIRQ_MASK 0x00010000
#define CAMIF_MD_FIFOFULL_MASK 0x00020000
#define CAMIF_MD_RAZ_FIFO_MASK 0x00040000
#define CAMIF_MD_REG_MASK 0x0007FFF8
// BUILDING of CAMIF_MD_MASK (=0x0007FFF8) //BIT 2:0 RESERVED
#define CAMIF_MD_MASK \
(((2<<(CAMIF_MD_ORDERCAMD_NUMB-1))-1)<<CAMIF_MD_ORDERCAMD_POS)|\
(((2<<(CAMIF_MD_ENVUP_NUMB-1))-1)<<CAMIF_MD_ENVUP_POS)|\
(((2<<(CAMIF_MD_ENVDOWN_NUMB-1))-1)<<CAMIF_MD_ENVDOWN_POS)|\
(((2<<(CAMIF_MD_ENHUP_NUMB-1))-1)<<CAMIF_MD_ENHUP_POS)|\
(((2<<(CAMIF_MD_ENHDOWN_NUMB-1))-1)<<CAMIF_MD_ENHDOWN_POS)|\
(((2<<(CAMIF_MD_DMA_NUMB-1))-1)<<CAMIF_MD_DMA_POS)|\
(((2<<(CAMIF_MD_THRESHOLD_NUMB-1))-1)<<CAMIF_MD_THRESHOLD_POS)|\
(((2<<(CAMIF_MD_ENIRQ_NUMB-1))-1)<<CAMIF_MD_ENIRQ_POS)|\
(((2<<(CAMIF_MD_FIFOFULL_NUMB-1))-1)<<CAMIF_MD_RAZ_FIFO_POS)|\
(((2<<(CAMIF_MD_RAZ_FIFO_NUMB-1))-1)<<CAMIF_MD_FIFOFULL_POS)
#define CAMIF_MD_RES_VAL\
((CAMIF_MD_ORDERCAMD_RES_VAL<<CAMIF_MD_ORDERCAMD_POS)|\
(CAMIF_MD_ENVUP_RES_VAL<<CAMIF_MD_ENVUP_POS)|\
(CAMIF_MD_ENVDOWN_RES_VAL<<CAMIF_MD_ENVDOWN_POS)|\
(CAMIF_MD_ENHUP_RES_VAL<<CAMIF_MD_ENHUP_POS)|\
(CAMIF_MD_ENHDOWN_RES_VAL<<CAMIF_MD_ENHDOWN_POS)|\
(CAMIF_MD_DMA_RES_VAL<<CAMIF_MD_DMA_POS)|\
(CAMIF_MD_THRESHOLD_RES_VAL<<CAMIF_MD_THRESHOLD_POS)|\
(CAMIF_MD_ENIRQ_RES_VAL<<CAMIF_MD_ENIRQ_POS)|\
(CAMIF_MD_FIFOFULL_RES_VAL<<CAMIF_MD_FIFOFULL_POS)|\
(CAMIF_MD_RAZ_FIFO_VAL<<CAMIF_MD_RAZ_FIFO_POS))
//Length values
//#define CAMIF_MD_CAMOSC_NUMB 1
//#define CAMIF_MD_IMGSIZE_NUMB 2
#define CAMIF_MD_ORDERCAMD_NUMB 1
#define CAMIF_MD_ENVUP_NUMB 1
#define CAMIF_MD_ENVDOWN_NUMB 1
#define CAMIF_MD_ENHUP_NUMB 1
#define CAMIF_MD_ENHDOWN_NUMB 1
#define CAMIF_MD_DMA_NUMB 1
#define CAMIF_MD_THRESHOLD_NUMB 7
#define CAMIF_MD_ENIRQ_NUMB 1
#define CAMIF_MD_RAZ_FIFO_NUMB 1
#define CAMIF_MD_FIFOFULL_NUMB 1
//Pos values
//#define CAMIF_MD_CAMOSC_POS 0x0
//#define CAMIF_MD_IMGSIZE_POS 0x1
#define CAMIF_MD_ORDERCAMD_POS 0x3
#define CAMIF_MD_ENVUP_POS 0x4
#define CAMIF_MD_ENVDOWN_POS 0x5
#define CAMIF_MD_ENHUP_POS 0x6
#define CAMIF_MD_ENHDOWN_POS 0x7
#define CAMIF_MD_DMA_POS 0x8
#define CAMIF_MD_THRESHOLD_POS 0x9
#define CAMIF_MD_ENIRQ_POS 0x10
#define CAMIF_MD_FIFOFULL_POS 0x11
#define CAMIF_MD_RAZ_FIFO_POS 0x12
//Reset values
//#define CAMIF_MD_CAMOSC_RES_VAL 0x0
//#define CAMIF_MD_IMGSIZE_RES_VAL 0x0
#define CAMIF_MD_ORDERCAMD_RES_VAL 0x0
#define CAMIF_MD_ENVUP_RES_VAL 0x0
#define CAMIF_MD_ENVDOWN_RES_VAL 0x0
#define CAMIF_MD_ENHUP_RES_VAL 0x0
#define CAMIF_MD_ENHDOWN_RES_VAL 0x0
#define CAMIF_MD_DMA_RES_VAL 0x0
#define CAMIF_MD_THRESHOLD_RES_VAL 0x01
#define CAMIF_MD_ENIRQ_RES_VAL 0x0
#define CAMIF_MD_FIFOFULL_RES_VAL 0x0
#define CAMIF_MD_RAZ_FIFO_VAL 0x0
// Status Register (Read Only)
//=============================
#ifdef __ES20__
#define CAMIF_SR_REG_OFFSET SET32BITS(0xC)
#else
#define CAMIF_SR_REG_OFFSET SET32BITS(0x03)
#endif
#define CAMIF_SR_REG (CAMIF_BASE_ADDRESS + CAMIF_SR_REG_OFFSET )
//Mask values
#define CAMIF_SR_VSTATUS_MASK 0x00000001
#define CAMIF_SR_HSTATUS_MASK 0x00000002
#define CAMIF_SR_REG_MASK 0x00000003
// building of CAMIF_SR_MASK (=0x00000003)
#define CAMIF_SR_MASK\
((((2<<(CAMIF_SR_VSTATUS_NUMB-1))-1)<<CAMIF_SR_VSTATUS_POS)|\
(((2<<(CAMIF_SR_HSTATUS_NUMB-1))-1)<<CAMIF_SR_HSTATUS_POS))
#define CAMIF_SR_RES_VAL\
((CAMIF_SR_VSTATUS_RES_VAL<<CAMIF_SR_VSTATUS_POS)|\
(CAMIF_SR_HSTATUS_RES_VAL<<CAMIF_SR_HSTATUS_POS))
//Length values
#define CAMIF_SR_VSTATUS_NUMB 1
#define CAMIF_SR_HSTATUS_NUMB 1
//Pos values
#define CAMIF_SR_VSTATUS_POS 0x0
#define CAMIF_SR_HSTATUS_POS 0x1
//Reset values
#define CAMIF_SR_VSTATUS_RES_VAL 0x0
#define CAMIF_SR_HSTATUS_RES_VAL 0x0
// Image Data Register (Read Only)
//=================================
#ifdef __ES20__
#define CAMIF_IMR_REG_OFFSET SET32BITS(0x10)
#else
#define CAMIF_IMR_REG_OFFSET SET32BITS(0x04)
#endif
#define CAMIF_IMR_REG (CAMIF_BASE_ADDRESS + CAMIF_IMR_REG_OFFSET )
#define CAMIF_IMR_REG_RES_VAL 0x00000000
// GPIO
//======
#ifdef __ES20__
#define CAMIF_GPIO_REG_OFFSET SET32BITS(0x14)
#else
#define CAMIF_GPIO_REG_OFFSET SET32BITS(0x05)
#endif
#define CAMIF_GPIO_REG (CAMIF_BASE_ADDRESS + CAMIF_GPIO_REG_OFFSET )
//Mask values
#define CAMIF_GPIO_CAMSER_MASK 0x00000001
#define CAMIF_GPIO_REG_MASK 0x00000001
// building of CAMIF_GPIO_MASK ( =0x00000001 )
#define CAMIF_GPIO_MASK \
(((2<<(CAMIF_GPIO_CAMSER_NUMB-1))-1)<<CAMIF_GPIO_CAMSER_POS)
#define CAMIF_GPIO_RES_VAL \
(CAMIF_GPIO_CAMSER_RES_VAL<<CAMIF_GPIO_CAMSER_POS)
//Length values
#define CAMIF_GPIO_CAMSER_NUMB 1
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