📄 usb_otg_hhc.h
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#define USB_OTG_HHC_HCINTERRUPTENABLE_32_RD_POS 3
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_RD_NUMB 1
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_RD_RES_VAL 0x0
//R/W1C
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SF_POS 2
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SF_NUMB 1
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SF_RES_VAL 0x0
//R/W1C
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_WDH_POS 1
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_WDH_NUMB 1
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_WDH_RES_VAL 0x0
//R/W1C
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SO_POS 0
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SO_NUMB 1
#define USB_OTG_HHC_HCINTERRUPTENABLE_32_SO_RES_VAL 0x0
//R/W1C
//USB_OTG_HHC_HCINTERUPTDISABLE
//-------------------
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0 REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCINTERUPTDISABLE_OFFSET*coeff16_arm+0)
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_MIE_POS 31
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_MIE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_MIE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_OC_POS 30
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_OC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_OC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RESERVED_POS 7
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RESERVED_NUMB 23
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RESERVED_RES_VAL 0x0
//R
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RHSC_POS 6
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RHSC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RHSC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_FNO_POS 5
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_FNO_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_FNO_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_UE_POS 4
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_UE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_UE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RD_POS 3
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RD_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_RD_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SF_POS 2
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SF_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SF_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_WDH_POS 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_WDH_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_WDH_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SO_POS 0
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SO_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_0_SO_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2 REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCINTERUPTDISABLE_OFFSET*coeff16_arm+2)
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_MIE_POS 31
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_MIE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_MIE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_OC_POS 30
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_OC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_OC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RESERVED_POS 7
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RESERVED_NUMB 23
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RESERVED_RES_VAL 0x0
//R
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RHSC_POS 6
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RHSC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RHSC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_FNO_POS 5
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_FNO_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_FNO_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_UE_POS 4
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_UE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_UE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RD_POS 3
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RD_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_RD_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SF_POS 2
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SF_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SF_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_WDH_POS 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_WDH_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_WDH_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SO_POS 0
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SO_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_16_2_SO_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32 REG32(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCINTERUPTDISABLE_OFFSET*coeff32_arm)
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_MIE_POS 31
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_MIE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_MIE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_OC_POS 30
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_OC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_OC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RESERVED_POS 7
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RESERVED_NUMB 23
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RESERVED_RES_VAL 0x0
//R
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RHSC_POS 6
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RHSC_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RHSC_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_FNO_POS 5
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_FNO_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_FNO_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_UE_POS 4
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_UE_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_UE_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RD_POS 3
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RD_NUMB 1
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_RD_RES_VAL 0x0
//R/WC
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_SF_POS 2
#define USB_OTG_HHC_HCINTERUPTDISABLE_32_SF_NUMB 1
#define USB_OTG_⌨️ 快捷键说明
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