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📄 usb_otg_hhc.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :usb_otg_hhc.h
//
//   Date of Module Modification:9/24/02
//   Date of Generation :9/24/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _USB_OTG_HHC__H
#define _USB_OTG_HHC__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define coeff8_arm   1
#define coeff16_arm  1
#define coeff32_arm  1

//-------------------

#define            USB_OTG_HHC_HCREVISION_OFFSET                                                                       0x000
#define            USB_OTG_HHC_HCCONTROL_OFFSET                                                                        0x004
#define            USB_OTG_HHC_HCCOMMANDSTATUS_OFFSET                                                                  0x008
#define            USB_OTG_HHC_HCINTERRUPTSTATUS_OFFSET                                                                0x00C
#define            USB_OTG_HHC_HCINTERRUPTENABLE_OFFSET                                                                0x010
#define            USB_OTG_HHC_HCINTERUPTDISABLE_OFFSET                                                                0x014
#define            USB_OTG_HHC_HCHCCA_OFFSET                                                                           0x018
#define            USB_OTG_HHC_HCPERIODCURRENTED_OFFSET                                                                0x01C
#define            USB_OTG_HHC_HCCONTROLHEADED_OFFSET                                                                  0x020
#define            USB_OTG_HHC_HCCONTROLCURRENTED_OFFSET                                                               0x024
#define            USB_OTG_HHC_HCBULKHEADED_OFFSET                                                                     0x028
#define            USB_OTG_HHC_HCBULKCURRENTED_OFFSET                                                                  0x02C
#define            USB_OTG_HHC_HCDONEHEAD_OFFSET                                                                       0x030
#define            USB_OTG_HHC_HCFMINTERVAL_OFFSET                                                                     0x034
#define            USB_OTG_HHC_HCFMREMAINING_OFFSET                                                                    0x038
#define            USB_OTG_HHC_HCFMNUMBER_OFFSET                                                                       0x03C
#define            USB_OTG_HHC_HCPERIODICSTART_OFFSET                                                                  0x040
#define            USB_OTG_HHC_HCLSTHRESHOLD_OFFSET                                                                    0x044
#define            USB_OTG_HHC_HCRHDESCRIPTORA_OFFSET                                                                  0x048
#define            USB_OTG_HHC_HCRHDESCRIPTORB_OFFSET                                                                  0x04C
#define            USB_OTG_HHC_HCRHSTATUS_OFFSET                                                                       0x050
#define            USB_OTG_HHC_HCRHPORTSTATUS1_OFFSET                                                                  0x054
#define            USB_OTG_HHC_HCRHPORTSTATUS2_OFFSET                                                                  0x058
#define            USB_OTG_HHC_HCRHPORTSTATUS3_OFFSET                                                                  0x05C
#define            USB_OTG_HHC_WHM_REVID_OFFSET                                                                        0x0F4
#define            USB_OTG_HHC_WHM_TEST_OBSV_OFFSET                                                                    0x0F8
#define            USB_OTG_HHC_WHM_TEST_CTL_OFFSET                                                                     0x0FC
#define            USB_OTG_HHC_HHC_TEST_CFG_OFFSET                                                                     0x100
#define            USB_OTG_HHC_HHC_TEST_CTL_OFFSET                                                                     0x104
#define            USB_OTG_HHC_HHC_TEST_OBSV_OFFSET                                                                    0x108
#define            USB_OTG_HHC_HHC_TEST_INITIATE_OFFSET                                                                0x10C
#define            USB_OTG_HHC_HHC_TEST_ADDR_OFFSET                                                                    0x110
#define            USB_OTG_HHC_HHC_TEST_WD1_OFFSET                                                                     0x114
#define            USB_OTG_HHC_HHC_TEST_WD2_OFFSET                                                                     0x118
#define            USB_OTG_HHC_HHC_TEST_WD3_OFFSET                                                                     0x11C
#define            USB_OTG_HHC_HHC_TEST_WD4_OFFSET                                                                     0x120
#define            USB_OTG_HHC_HHC_TEST_RD1_OFFSET                                                                     0x124
#define            USB_OTG_HHC_HHC_TEST_RD2_OFFSET                                                                     0x128
#define            USB_OTG_HHC_HHC_TEST_RD3_OFFSET                                                                     0x12C
#define            USB_OTG_HHC_HHC_TEST_RD4_OFFSET                                                                     0x130




//USB_OTG_HHC_HCREVISION
//-------------------
#define            USB_OTG_HHC_HCREVISION_16_0                                                                         REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCREVISION_OFFSET*coeff16_arm+0)


#define            USB_OTG_HHC_HCREVISION_16_0_RESERVED_POS                                                              8
#define            USB_OTG_HHC_HCREVISION_16_0_RESERVED_NUMB                                                             24
#define            USB_OTG_HHC_HCREVISION_16_0_RESERVED_RES_VAL                                                          0x0
//R

#define            USB_OTG_HHC_HCREVISION_16_0_REV_POS                                                                   0
#define            USB_OTG_HHC_HCREVISION_16_0_REV_NUMB                                                                  8
#define            USB_OTG_HHC_HCREVISION_16_0_REV_RES_VAL                                                               0x10
//R

#define            USB_OTG_HHC_HCREVISION_16_2                                                                         REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCREVISION_OFFSET*coeff16_arm+2)


#define            USB_OTG_HHC_HCREVISION_16_2_RESERVED_POS                                                              8
#define            USB_OTG_HHC_HCREVISION_16_2_RESERVED_NUMB                                                             24
#define            USB_OTG_HHC_HCREVISION_16_2_RESERVED_RES_VAL                                                          0x0
//R

#define            USB_OTG_HHC_HCREVISION_16_2_REV_POS                                                                   0
#define            USB_OTG_HHC_HCREVISION_16_2_REV_NUMB                                                                  8
#define            USB_OTG_HHC_HCREVISION_16_2_REV_RES_VAL                                                               0x10
//R

#define            USB_OTG_HHC_HCREVISION_32                                                                           REG32(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCREVISION_OFFSET*coeff32_arm)


#define            USB_OTG_HHC_HCREVISION_32_RESERVED_POS                                                                8
#define            USB_OTG_HHC_HCREVISION_32_RESERVED_NUMB                                                               24
#define            USB_OTG_HHC_HCREVISION_32_RESERVED_RES_VAL                                                            0x0
//R

#define            USB_OTG_HHC_HCREVISION_32_REV_POS                                                                     0
#define            USB_OTG_HHC_HCREVISION_32_REV_NUMB                                                                    8
#define            USB_OTG_HHC_HCREVISION_32_REV_RES_VAL                                                                 0x10
//R


//USB_OTG_HHC_HCCONTROL
//-------------------
#define            USB_OTG_HHC_HCCONTROL_16_0                                                                          REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCCONTROL_OFFSET*coeff16_arm+0)


#define            USB_OTG_HHC_HCCONTROL_16_0_RESERVED_POS                                                               11
#define            USB_OTG_HHC_HCCONTROL_16_0_RESERVED_NUMB                                                              21
#define            USB_OTG_HHC_HCCONTROL_16_0_RESERVED_RES_VAL                                                           0x0
//R

#define            USB_OTG_HHC_HCCONTROL_16_0_RWE_POS                                                                    10
#define            USB_OTG_HHC_HCCONTROL_16_0_RWE_NUMB                                                                   1
#define            USB_OTG_HHC_HCCONTROL_16_0_RWE_RES_VAL                                                                0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_RWC_POS                                                                    9
#define            USB_OTG_HHC_HCCONTROL_16_0_RWC_NUMB                                                                   1
#define            USB_OTG_HHC_HCCONTROL_16_0_RWC_RES_VAL                                                                0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_IR_POS                                                                     8
#define            USB_OTG_HHC_HCCONTROL_16_0_IR_NUMB                                                                    1
#define            USB_OTG_HHC_HCCONTROL_16_0_IR_RES_VAL                                                                 0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_HCFS_POS                                                                   6
#define            USB_OTG_HHC_HCCONTROL_16_0_HCFS_NUMB                                                                  2
#define            USB_OTG_HHC_HCCONTROL_16_0_HCFS_RES_VAL                                                               0x00
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_BLE_POS                                                                    5
#define            USB_OTG_HHC_HCCONTROL_16_0_BLE_NUMB                                                                   1
#define            USB_OTG_HHC_HCCONTROL_16_0_BLE_RES_VAL                                                                0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_CLE_POS                                                                    4
#define            USB_OTG_HHC_HCCONTROL_16_0_CLE_NUMB                                                                   1
#define            USB_OTG_HHC_HCCONTROL_16_0_CLE_RES_VAL                                                                0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_IE_POS                                                                     3
#define            USB_OTG_HHC_HCCONTROL_16_0_IE_NUMB                                                                    1
#define            USB_OTG_HHC_HCCONTROL_16_0_IE_RES_VAL                                                                 0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_PLE_POS                                                                    2
#define            USB_OTG_HHC_HCCONTROL_16_0_PLE_NUMB                                                                   1
#define            USB_OTG_HHC_HCCONTROL_16_0_PLE_RES_VAL                                                                0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_0_CBSR_POS                                                                   0
#define            USB_OTG_HHC_HCCONTROL_16_0_CBSR_NUMB                                                                  2
#define            USB_OTG_HHC_HCCONTROL_16_0_CBSR_RES_VAL                                                               0x0
//R/W

#define            USB_OTG_HHC_HCCONTROL_16_2                                                                          REG16(USB_OTG_HHC_BASE_ADDR_ARM+USB_OTG_HHC_HCCONTROL_OFFSET*coeff16_arm+2)

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