spi100khz.h

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/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : spi_100khz.h

   Description          : Header file for the Serial Port Interface

   Project              : Perseus

   Author               : Sebastien SABATIER

   FUNCTIONS PROVIDED	:
			  SPI_100khzTestResetValue
			  SPI_100khzInitSet1
			  SPI_100khzInitSet2
			  SPI_100khzInitCTRL
			  SPI_100khzWriteLsb
			  SPI_100khzWriteMsb
			  SPI_100khz_read_LSB
			  SPI_100khz_read_MSB
			  SPI_100khz_read_Status
			  SPI_100khzIsReadEnd
			  SPI_100khzIsWriteEnd
			  SPI_100khzStartClock
			  SPI_100khzStopClock

===============================================================================
*/

#ifndef _SPI_100KHZ__HH
#define _SPI_100KHZ__HH

// include files
#include "global_types.h"
#include "mapping.h"
#include "result.h"

// Identification of SPI modules
// *WARNING* :  module ID <=> its base address
typedef enum {
    SPI_MODULE_1        = SPI_100K_1_BASE_ADDR_ARM,
    SPI_MODULE_2        = SPI_100K_2_BASE_ADDR_ARM
} SPI_module_t;

// define registers mapping
#define SPI_100KHZ_SET1_OFFSET   0x000
#define SPI_100KHZ_SET2_OFFSET   0x002
#define SPI_100KHZ_CTRL_OFFSET   0x004
#define SPI_100KHZ_STATUS_OFFSET 0x006
#define SPI_100KHZ_TX_LSB_OFFSET 0x008
#define SPI_100KHZ_TX_MSB_OFFSET 0x00A
#define SPI_100KHZ_RX_LSB_OFFSET 0x00C
#define SPI_100KHZ_RX_MSB_OFFSET 0x00E

/*
-----------------------------------------------------------------------------
 NAME        : SPI__REG_ADDR/SPI__REG_PTR.                                  -
 DESCRIPTION : Macros returning the absolute address (SPI__REG_ADDR)        -
               or the associated pointer (SPI__REG_PTR) of a register       -
               in a SPI module.                                             -
               Test the access of the register to the SPI_100K_<module>.    -
 PARAMETERS  :                                                              -
   Module   => SPI module.                                                  -
   Reg      => base register name (relative).                               -
 RETURN VALUE: absolute address/pointer.                                    -
 LIMITATIONS : it's a macro using strings fusion operator (##)              -
-----------------------------------------------------------------------------
*/
#define SPI__REG_ADDR( Module, Reg)\
    ((Module) + SPI_100KHZ_##Reg##_OFFSET)
#define SPI__REG_PTR( Module, Reg)\
    ((REGISTER_UWORD16*)(SPI__REG_ADDR (Module, Reg)))

// Kept for compatibility : absolute addresses of SPI module 1 registers
#define SPI_100KHZ_SET1_ADDR    SPI__REG_ADDR(SPI_MODULE_1,SET1)
#define SPI_100KHZ_SET2_ADDR    SPI__REG_ADDR(SPI_MODULE_1,SET2)
#define SPI_100KHZ_CTRL_ADDR    SPI__REG_ADDR(SPI_MODULE_1,CTRL)
#define SPI_100KHZ_STATUS_ADDR  SPI__REG_ADDR(SPI_MODULE_1,STATUS)
#define SPI_100KHZ_TX_LSB_ADDR  SPI__REG_ADDR(SPI_MODULE_1,TX_LSB)
#define SPI_100KHZ_TX_MSB_ADDR  SPI__REG_ADDR(SPI_MODULE_1,TX_MSB)
#define SPI_100KHZ_RX_LSB_ADDR  SPI__REG_ADDR(SPI_MODULE_1,RX_LSB)
#define SPI_100KHZ_RX_MSB_ADDR  SPI__REG_ADDR(SPI_MODULE_1,RX_MSB)

// define mask register
#define SPI_100KHZ_SET1_REG_MASK          0x003F
#define SPI_100KHZ_SET1_EN_CLK_MASK       0x0001
#define SPI_100KHZ_SET1_REG_RESET_VALUE   0x0030

#define SPI_100KHZ_SET2_REG_MASK          0x7fff
#define SPI_100KHZ_SET2_REG_RESET_VALUE   0x0000

#define SPI_100KHZ_CTRL_REG_MASK          0x03ff
#define SPI_100KHZ_CTRL_REG_RESET_VALUE   0x0000

#define SPI_100KHZ_STATUS_REG_MASK        0x0003
#define SPI_100KHZ_STATUS_RE_MASK         0x0001
#define SPI_100KHZ_STATUS_WE_MASK         0x0002
#define SPI_100KHZ_STATUS_REG_RESET_VALUE 0x0000
#define SPI_100KHZ_STATUS_BUSY_VALUE      0x00

#define SPI_100KHZ_TX_LSB_REG_RESET_VALUE 0x0000
#define SPI_100KHZ_TX_MSB_REG_RESET_VALUE 0x0000

#define SPI_100KHZ_RX_LSB_REG_RESET_VALUE 0x0000
#define SPI_100KHZ_RX_MSB_REG_RESET_VALUE 0x0000

// define position bit fields
#define SPI_100KHZ_SET1_PTV_POSBIT   1
#define SPI_100KHZ_SET1_MSK0_POSBIT  4
#define SPI_100KHZ_SET1_MSK1_POSBIT  5

#define SPI_100KHZ_SET2_P_POSBIT     5
#define SPI_100KHZ_SET2_L_POSBIT    10

#define SPI_100KHZ_CTRL_WR_POSBIT    1
#define SPI_100KHZ_CTRL_NB_POSBIT    2
#define SPI_100KHZ_CTRL_AD_POSBIT    7


// define types
typedef enum
{
  SPI_100KHZ_READ_ACTION,
  SPI_100KHZ_WRITE_ACTION
} SPI_100KHZ_Action_t;

typedef void (*SPI_100KHZ_END) (SPI_100KHZ_Action_t Action);

typedef enum
{
  SPI_100KHZ_SET1_REG_RESET_ERROR = 3,
  SPI_100KHZ_SET2_REG_RESET_ERROR,
  SPI_100KHZ_CTRL_REG_RESET_ERROR,
  SPI_100KHZ_STATUS_REG_RESET_ERROR,
  SPI_100KHZ_TX_LSB_REG_RESET_ERROR,
  SPI_100KHZ_TX_MSB_REG_RESET_ERROR,
  SPI_100KHZ_RX_LSB_REG_RESET_ERROR,
  SPI_100KHZ_RX_MSB_REG_RESET_ERROR,

  SPI_100KHZ_SET1_REG_ACCESS_ERROR,
  SPI_100KHZ_SET2_REG_ACCESS_ERROR,
  SPI_100KHZ_CTRL_REG_ACCESS_ERROR,

  SPI_100KHZ_TX_LSB_REG_ACCESS_ERROR,
  SPI_100KHZ_TX_MSB_REG_ACCESS_ERROR
} SPI_100KHZ_Error_t;

//Clock Enable toggle
typedef enum
{
  SPI_100KHZ_SHUT_OFF_CLOCK = 0,
  SPI_100KHZ_RUN_CLOCK      = 1
} SPI_100KHZ_EnableClock_t;

//Pres-scale clock divisor
typedef enum
{
  SPI_100KHZ_SET1_PTV1   = 0,
  SPI_100KHZ_SET1_PTV2   = 1,
  SPI_100KHZ_SET1_PTV4   = 2,
  SPI_100KHZ_SET1_PTV8   = 3,
  SPI_100KHZ_SET1_PTV16  = 4,
  SPI_100KHZ_SET1_PTV32  = 5,
  SPI_100KHZ_SET1_PTV64  = 6,
  SPI_100KHZ_SET1_PTV128 = 7
} SPI_100KHZ_Ptv_t;

//Enable Interrupt for Write Cycle
typedef enum
{
  SPI_100KHZ_ENABLE_IT_WRITE  = 0,
  SPI_100KHZ_DISABLE_IT_WRITE = 1
} SPI_100KHZ_MaskIntWr_t;

//Enable Interrupt for Read/Write Cycle
typedef enum
{
  SPI_100KHZ_ENABLE_IT_READWRITE  = 0,
  SPI_100KHZ_DISABLE_IT_READWRITE = 1
} SPI_100KHZ_MaskIntRdWr_t;

typedef enum
{
  SPI_100KHZ_DEV0_FALLING_EDGE_CLOCK = 0,
  SPI_100KHZ_DEV1_FALLING_EDGE_CLOCK = 0,
  SPI_100KHZ_DEV2_FALLING_EDGE_CLOCK = 0,
  SPI_100KHZ_DEV3_FALLING_EDGE_CLOCK = 0,
  SPI_100KHZ_DEV4_FALLING_EDGE_CLOCK = 0,

  SPI_100KHZ_DEV0_RISING_EDGE_CLOCK  = 1,
  SPI_100KHZ_DEV1_RISING_EDGE_CLOCK  = 2,
  SPI_100KHZ_DEV2_RISING_EDGE_CLOCK  = 4,
  SPI_100KHZ_DEV3_RISING_EDGE_CLOCK  = 8,
  SPI_100KHZ_DEV4_RISING_EDGE_CLOCK  = 16
} SPI_100KHZ_EdgeClock_t;

//Format of enable signals nTSPEN P(ositive)
typedef enum
{
  SPI_100KHZ_DEV0_NEGATIVE_LEVEL_SIG = 0,
  SPI_100KHZ_DEV1_NEGATIVE_LEVEL_SIG = 0,
  SPI_100KHZ_DEV2_NEGATIVE_LEVEL_SIG = 0,
  SPI_100KHZ_DEV3_NEGATIVE_LEVEL_SIG = 0,
  SPI_100KHZ_DEV4_NEGATIVE_LEVEL_SIG = 0,

  SPI_100KHZ_DEV0_POSITIVE_LEVEL_SIG = 1,
  SPI_100KHZ_DEV1_POSITIVE_LEVEL_SIG = 2,
  SPI_100KHZ_DEV2_POSITIVE_LEVEL_SIG = 4,
  SPI_100KHZ_DEV3_POSITIVE_LEVEL_SIG = 8,
  SPI_100KHZ_DEV4_POSITIVE_LEVEL_SIG = 16
} SPI_100KHZ_Ptspen_t;

//Format of enable signals nTSPEN L(evel)
typedef enum
{
  SPI_100KHZ_DEV0_LEVEL_TRIGGER_SIG = 0,
  SPI_100KHZ_DEV1_LEVEL_TRIGGER_SIG = 0,
  SPI_100KHZ_DEV2_LEVEL_TRIGGER_SIG = 0,
  SPI_100KHZ_DEV3_LEVEL_TRIGGER_SIG = 0,
  SPI_100KHZ_DEV4_LEVEL_TRIGGER_SIG = 0,

  SPI_100KHZ_DEV0_EDGE_TRIGGER_SIG  = 1,
  SPI_100KHZ_DEV1_EDGE_TRIGGER_SIG  = 2,
  SPI_100KHZ_DEV2_EDGE_TRIGGER_SIG  = 4,
  SPI_100KHZ_DEV3_EDGE_TRIGGER_SIG  = 8,
  SPI_100KHZ_DEV4_EDGE_TRIGGER_SIG  = 16
} SPI_100KHZ_Ltspen_t;

//Read and write process activation set 0 and 1
typedef enum
{
  SPI_100KHZ_DEACTIV_RDWR_PROCESS = 0,
  SPI_100KHZ_ACTIV_RDWR_PROCESS   = 1
} SPI_100KHZ_CtrlRd_t;

//Write process activation set 0 and 1
typedef enum
{
  SPI_100KHZ_DEACTIV_WR_PROCESS = 0,
  SPI_100KHZ_ACTIV_WR_PROCESS   = 1
} SPI_100KHZ_CtrlWr_t;

//Transmission Length  Word size (from 1 to 32 )
typedef enum
{
  SPI_100KHZ_CTRL_NB_1  = 0x00, // One Bit Transmit
  SPI_100KHZ_CTRL_NB_2,         // Two bits transmit
  SPI_100KHZ_CTRL_NB_3,  SPI_100KHZ_CTRL_NB_4,  SPI_100KHZ_CTRL_NB_5,
  SPI_100KHZ_CTRL_NB_6,  SPI_100KHZ_CTRL_NB_7,  SPI_100KHZ_CTRL_NB_8,
  SPI_100KHZ_CTRL_NB_9,  SPI_100KHZ_CTRL_NB_10, SPI_100KHZ_CTRL_NB_11,
  SPI_100KHZ_CTRL_NB_12, SPI_100KHZ_CTRL_NB_13, SPI_100KHZ_CTRL_NB_14,