interrupt_mapping.h~

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· H~ 代码 · 共 130 行

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 2000, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//===============================================================================

#ifndef _INTERRUPT_MAPPING_H_
#define _INTERRUPT_MAPPING_H_

#ifndef DOLO_DC 
/* -------------------*/
/* INTERRUPTS LEVEL 1 */
/* -------------------*/

#define   LEV2_IRQ_INT               0  
#define   CAM_CORE_INT               1  
#define   LEV2_FIQ_INT               2
// IRQ_3 unused  
#define   MCBSP_DIGITAL_RF_TX        4  
#define   MCBSP_DIGITAL_RF_RX        5
#define   RTDX_INT	             6  
#define   DSP_MMU_ABORT_INT          7  
#define   HOST_INT           	     8  
#define   ABORT_INT                  9  
#define   DSP_MAILBOX1_INT           10 
#define   DSP_MAILBOX2_INT           11 
#define   LCD_LINE_INT               12 
#define   PRIVATE_RHEA_ABORT_INT     13
#define   IRQ1_GPIO1_INT             14 
#define   UART3_INT                  15 
#define   TIMER3_INT                 16 
#define   GPTIMER1_INT               17 
#define   GPTIMER2_INT               18 
#define   DMA_CH0_INT	             19 
#define   DMA_CH1_INT                20 
#define   DMA_CH2_INT                21 
#define   DMA_CH3_INT                22 
#define   DMA_CH4_INT                23 
#define   DMA_CH5_INT                24 
#define   DMA_CH_LCD_INT             25 
#define   TIMER1_INT                 26 
#define   WD_TIMER_INT               27 
#define   PUBLIC_RHEA_ABORT_INT      28
#define   EXT_IRQ_INT                29
#define   TIMER2_INT                 30 
#define   LCD_CTRL_INT               31 

/* ----------------------------------------------*/
/* INTERRUPTS LEVEL 2                            */
/* A 32 offset is added (i.e FAC IT (level 2 #0) */
/* has number 32)                                */
/* ----------------------------------------------*/

#define   FAC_INT                    32 
#define   KEYBOARD_INT               33 
#define   UWIRE_TX_INT               34 
#define   UWIRE_RX_INT               35 
#define   I2C_1_INT                  36 
#define   GEA_INT                    37 
#define   USB_HHC1_INT               38 
#define   USB_HHC2_INT	   	     39 
#define   USB_OTG_INT                40 
#define   TSP_RX_INT                 41 
// IRQ_42 free
// IRQ_43 free 
#define   MCBSP1_TX_INT              44 
#define   MCBSP1_RX_INT              45 
#define   UART1_INT                  46 
#define   UART2_INT                  47 
#define   MCSI1_TX_RX_RST_FRAMEERROR_INT 48 
#define   MCSI2_TX_RX_RST_FRAMEERROR_INT 49 
#define   TPU_ITF                    50  // TPU IRQN(0) ITF		
#define   TPU_ITP                    51  // TPU IRQN(1) ITP		
#define   USB_GENI_INT               52 
#define   ONE_WIRE_INT         	     53 
#define   OSTIMER32K_INT             54 
#define   MMCSDIO1_INT	             55 
#define   ULPD_32KGAUGING_INT        56 
#define   USIM_INT                   57 
#define   DIGITAL_RF_INT             58 
#define   MS_INT                     59 
#define   DSP_MMU_INT                60
#define   USB_ISO_ON_INT             61 
#define   USB_NON_ISO_ON_INT         62 
#define   I2C_2_INT                  63		
#define   ULPD_GSM_TIMER_INT         64		
#define   CIPHER_INT                 65
// IRQ_66 unused
#define   RNG_INT                    67 
#define   RNG_IDLE_INT               68 
#define   RHEA_SWITH_ERROR_INT       69 
// IRQ_70  unused
// IRQ_71 unused 
#define   IRQ1_GPIO2_INT             72 
// IRQ_73  unused
#define   MMCSDIO2_INT               74 
// IRQ_75  unused
#define   COMM_RX_INT                76
#define   COMM_TX_INT                77
#define   PERIPH_WAKEUP_INT          78
#define   PKA_INT                    79
#defien   ELCD_DMA_LCD_ABORT_INT     80
#define   SPI_INT                    81 
#define   ELCD_TX_INT                82 
#define   ELCD_RX_INT                83 
#define   SHA1_MD5_INT               84 
#define   IRQ_DMA_CH6_INT            85
#define   IRQ_DMA_CH7_INT            86
#define   IRQ_DMA_CH8_INT            87
#define   IRQ_DMA_CH9_INT            88
#define   IRQ_DMA_CH10_INT           89
#define   IRQ_DMA_CH11_INT           90
#define   IRQ_DMA_CH12_INT           91
#define   IRQ_DMA_CH13_INT           92
#define   IRQ_DMA_CH14_INT           93
#define   IRQ_DMA_CH15_INT           94
#define   NANDFLASH_INT              95
//  96: FREE
// ...
// 159: FREE

#endif
#endif