led_common.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 537 行 · 第 1/2 页
H
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/* -----------------------------------------------------------------------------
NAME : ARM9_SET_R_BIT
DESCRIPTION : Set R Bit
using ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_SET_R_BIT \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp |= R_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM9_RESET_R_BIT
DESCRIPTION : Clear R Bit
using ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_RESET_R_BIT \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp &= ~R_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM9_DCACHE_ON
DESCRIPTION : Enable Data Cache of ARM926EJ-S using
ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_DCACHE_ON \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp |= C_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM9_ICACHE_ON
DESCRIPTION : Enable Instruction Cache of ARM926EJ-S using
ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_ICACHE_ON \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp |= I_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM9_DCACHE_OFF
DESCRIPTION : Disable Data Cache of ARM926EJ-S using
ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_DCACHE_OFF \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp &= ~C_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM9_ICACHE_OFF
DESCRIPTION : Disable Instruction Cache of ARM926EJ-S using
ARM_WR_CNTRL and ARM_RD_CNTRL functions
PARAMETERS : None.
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_ICACHE_OFF \
{ \
int tmp; \
\
tmp = ARM_RD_CNTRL(); \
tmp &= ~I_bit; \
ARM_WR_CNTRL(tmp); \
}
/* -----------------------------------------------------------------------------
NAME : ARM_WR_TTBR
DESCRIPTION : Write value into CP15 register2 (used to set TTB)
PARAMETERS : See ARM926EJ-S CP15 Register 2 specification
RETURN VALUE: None.
LIMITATIONS : None.
----------------------------------------------------------------------------- */
extern void ARM_WR_TTBR (int value);
/* -----------------------------------------------------------------------------
NAME : ARM_RD_TTBR -
DESCRIPTION : Read value from CP15 register2 (used to set TTB) -
PARAMETERS : See ARM926EJ-S CP15 Register 2 specification -
RETURN VALUE: Translation Table base value -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern int ARM_RD_TTBR (void);
/* -----------------------------------------------------------------------------
NAME : ARM_WR_DOMAIN_REG -
DESCRIPTION : Write value into CP15 register3 (used to set domain register)-
PARAMETERS : See ARM926EJ-S CP15 Register 3 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern void ARM_WR_DOMAIN_REG (int value);
/* -----------------------------------------------------------------------------
NAME : ARM_RD_DOMAIN_REG -
DESCRIPTION : Read value from CP15 register3 (used to set domain register) -
PARAMETERS : See ARM926EJ-S CP15 Register 3 specification -
RETURN VALUE: Domain Register value -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern int ARM_RD_DOMAIN_REG (void);
/* -----------------------------------------------------------------------------
NAME : ARM_FLUSH_CACHE -
DESCRIPTION : Flush I_Cache and D_Cache -
PARAMETERS : See ARM926EJ-S CP15 Register 7 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern void ARM_FLUSH_CACHE (void);
/* -----------------------------------------------------------------------------
NAME : ARM_DRAIN_WR_BUFFER -
DESCRIPTION : Write Buffer drain to external memory -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern void ARM_DRAIN_WR_BUFFER (void);
/* -----------------------------------------------------------------------------
NAME : ARM_WAIT_INT_WBUFFER -
DESCRIPTION : -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
extern void ARM_WAIT_INT_WBUFFER (void);
/*-----------------------------------------------------------------------------
NAME : ARM_Section -
DESCRIPTION : Build 1st level descriptor and address of this descriptor -
Write this descriptor into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, access permission bit-
domain used, Cacheable and Bufferable bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
----------------------------------------------------------------------------- */
#define ARM_Section(PA, VA, TTB, ap, domain, CB ) \
{ \
int add_D1, val_D1; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((PA & 0xFFF00000) | (ap << 10) | (domain << 5) |(CB << 2) | 0x2); \
\
*(UWORD32*)add_D1 = val_D1; \
}
/*------------------------------------------------------------------------------
NAME : ARM_LargePage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------*/
#define ARM_LargePage(PA, VA, TTB, page_base,\
ap0, ap1, ap2, ap3, domain, CB) \
{ \
int add_D1, val_D1; \
int add_D2, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFFC00) | (domain << 5) | 0x1); \
\
add_D2 = ((page_base & 0xFFFFFC00) | (((VA & 0x000FF000) >> 12) << 2)); \
val_D2 = ((PA & 0xFFFF0000) | (ap3 << 10) | (ap2 << 8) | (ap1 << 6) |\
(ap0 << 4) | (CB << 2) | 0x1);\
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
/*------------------------------------------------------------------------------
NAME : ARM_SmallPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------*/
#define ARM_SmallPage(PA, VA, TTB, page_base, \
ap0, ap1, ap2, ap3, domain, CB) \
{ \
int add_D1, val_D1; \
int add_D2, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFFC00) | (domain << 5) | 0x1); \
\
add_D2 = ((page_base & 0xFFFFFC00) | (((VA & 0x000FF000) >> 12) << 2)); \
val_D2 = ((PA & 0xFFFFF000) | (ap3 << 10) | (ap2 << 8) | (ap1 << 6) |\
(ap0 << 4) | (CB << 2) | 0x2); \
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
/*------------------------------------------------------------------------------
NAME : ARM_TinyPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------*/
#define ARM_TinyPage(PA, VA, TTB, page_base, ap, domain, CB) \
{ \
int add_D1, add_D2; \
int val_D1, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFF000) | (domain << 5) | 0x3); \
\
add_D2 = ((page_base & 0xFFFFF000) | (((VA & 0x000FFC00) >> 10) << 2)); \
val_D2 = ((PA & 0xFFFFFC00) | (ap << 4) | (CB << 2) | 0x3); \
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
#endif /* _HEL2_COMMON_ASM_LED__HH */
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