led_common.h

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/*==============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments. For Unrestricted Internal Use Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.
//   Created 2002, (C) Copyright 2002 Texas Instruments.  All rights reserved.
//
//   Created	      : 29th of July, 2002, 5.00pm
//
//   Filename           : hel_common_asm_led.h
//
//   Description        : Header file for common LED ARM926EJS assembler programs
//
//   Project            : HELEN2, OMAP1610
//
//   Author             : Dayo Adeyeye
//
//   FUNCTIONS PROVIDED :
//
//		extern void DumpStop_LED(UWORD16 ledsig);
//
//		extern void SetARM_WFI_sleep( UWORD32 gpio_base_addr,
//					   UWORD16 execpin);
//
//		CP15 Register1: Control register
//
//                      ARM_WR_CNTRL                (external function)
//                      ARM_RD_CNTRL                (external function)
//			ARM9_MMU_ON
//			ARM9_MMU_DCACHE_OFF
//			ARM9_MMU_OFF_ONLY
//			ARM9_SET_ALIGNMENT_BIT
//			ARM9_SET_BIG_ENDIAN
//			ARM9_SET_LITTLE_ENDIAN
//			ARM9_SET_S_BIT
//			ARM9_RESET_S_BIT
//			ARM9_SET_R_BIT
//			ARM9_RESET_R_BIT
//			ARM9_DCACHE_ON
//			ARM9_ICACHE_ON
//			ARM9_DCACHE_OFF
//			ARM9_ICACHE_OFF
//
//		CP15 Register2:  Translation Table Base Register
//
//                      ARM_WR_TTBR                 (external function)
//
//		CP15 Register3:  Domain Access Control Register
//
//                      ARM_WR_DOMAIN_REG           (external function)
//
//
============================================================================= */

#ifndef _LED_COMMON__HH
#define _LED_COMMON__HH

#include "global_types.h"

extern void DumpStop_LED(UWORD16 ledsig);

extern void SetARM_WFI_sleep(UWORD32 gpio_base_addr,
			     UWORD16 execpin);

#define LED_RES_DPLL_TIMEOUT   0xDEAF
#define LED_RES_LDO_TIMEOUT    0xFADE
#define LED_RES_LED_TIMEOUT    0xCEED
#define LED_RES_BAD_DEVICE     0xBADD
#define LED_RES_NORMAL_BOOT    0xABCD

/* Constants used to identify bits in the CP15 Reg1 Control Reg */
#define M_bit	0x1	/* MMU Enable Address translation & page access */
#define A_bit	0x2	/* Alignment fault enable/disable */
#define C_bit	0x4	/* Data cache enable/disable */
#define B_bit   0x80	/* Big(1)/Little(0) Endian configuration */
#define S_bit	0x100	/* System protection bit */
#define R_bit	0x200	/* ROM protection bit */
#define I_bit	0x1000	/* Instruction Cache enable/disable */
#define V_bit	0x2000	/* Alternate Vectors select bit */
#define RR_bit	0x4000	/* Random(0)/Round Robin(1) cache configuration */
#define L4_bit	0x8000	/* LDR PC, Set T(0)/Do not set T(1) configuration */

/* Constants used to enable cacheable & bufferable memory regions */
#define CACHEABLE  2
#define BUFFERABLE 1

/* Access Permissions - not shifted into position */
#define NO_ACCESS  0 
#define SVC_R      0
#define SVC_RW     1
#define NO_USR_W   2
#define ALL_ACCESS 3

#define DOMAIN0	   0
#define DOMAIN1	   1
#define DOMAIN2	   2
#define DOMAIN3	   3
#define DOMAIN4	   4
#define DOMAIN5	   5
#define DOMAIN6	   6
#define DOMAIN7	   7
#define DOMAIN8	   8
#define DOMAIN9	   9
#define DOMAIN10   10
#define DOMAIN11   11
#define DOMAIN12   12
#define DOMAIN13   13
#define DOMAIN14   14
#define DOMAIN15   15

/* -----------------------------------------------------------------------------
 NAME        : ARM_WR_CNTRL(r0)
 DESCRIPTION : Write value into CP15 register1 (used to enable/disable MMU,
               Instruction & Data Cache. Cfg Endian, Protection, INT ...
 PARAMETERS  : See ARM926EJ-S CP15 Register 1 specification
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
extern void ARM_WR_CNTRL (int value);

/* -----------------------------------------------------------------------------
 NAME        : ARM_RD_CNTRL
 DESCRIPTION : Write value into CP15 register1 (used to enable/disable MMU,
               Instruction & Data Cache. Cfg Endian, Protection, INT ...
 PARAMETERS  : See ARM926EJ-S CP15 Register 1 specification
 RETURN VALUE: value of CP15 register1 (contained in register R0)
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
extern int ARM_RD_CNTRL (void);

/* -----------------------------------------------------------------------------
 NAME        : ARM9_MMU_ON
 DESCRIPTION : Enable MMU of ARM926EJ-S using
               ARM_WR_CNTRL and ARM_RD_CNTRL functions
 PARAMETERS  : None.
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_MMU_ON     \
{                       \
   int tmp;              \
                          \
   tmp = ARM_RD_CNTRL(); \
   tmp |= M_bit;            \
   ARM_WR_CNTRL(tmp);     \
}


/* -----------------------------------------------------------------------------
 NAME        : ARM9_MMU_DCACHE_OFF                                           -
 DESCRIPTION : Disable MMU and Data Cache of ARM926EJ-S using               -
               ARM_WR_CNTRL and ARM_RD_CNTRL functions                 -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
----------------------------------------------------------------------------- */
#define ARM9_MMU_DCACHE_OFF \
{ \
   int tmp; \
   \
   ARM9_DCACHE_OFF; \
   tmp = ARM_RD_CNTRL(); \
   tmp &= ~M_bit; \
   ARM_WR_CNTRL(tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_MMU_OFF_ONLY
 DESCRIPTION : Only switch off MMU of ARM926EJ-S using
               ARM_WR_CNTRL and ARM_RD_CNTRL functions
 PARAMETERS  : None.
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_MMU_OFF_ONLY \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp &= ~M_bit; \
   ARM_WR_CNTRL(int tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_SET_ALIGNMENT_BIT                                        -
 DESCRIPTION : Set Alignment bit using                                      -
               ARM_WR_CNTRL and ARM_RD_CNTRL functions                 -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
----------------------------------------------------------------------------- */
#define ARM9_SET_ALIGNMENT_BIT \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp |= A_bit; \
   ARM_WR_CNTRL(tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_SET_BIG_ENDIAN                                           -
 DESCRIPTION : Set Big Endian Mode using                                    -
               ARM_WR_CNTRL and ARM_RD_CNTRL functions                 -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
----------------------------------------------------------------------------- */
#define ARM9_SET_BIG_ENDIAN \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp |= B_bit; \
   ARM_WR_CNTRL(tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_SET_LITTLE_ENDIAN
 DESCRIPTION : Set Little endian mode (default mode) using
               ARM_WR_CNTRL and ARM_RD_CNTRL functions
 PARAMETERS  : None.
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_SET_LITTLE_ENDIAN \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp &= ~B_bit; \
   ARM_WR_CNTRL(tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_SET_S_BIT
 DESCRIPTION : Set S Bit using
               ARM_WR_CNTRL and ARM_RD_CNTRL functions
 PARAMETERS  : None.
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_SET_S_BIT \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp |= S_bit; \
   ARM_WR_CNTRL(tmp); \
}

/* -----------------------------------------------------------------------------
 NAME        : ARM9_RESET_S_BIT
 DESCRIPTION : Clear S Bit
               using ARM_WR_CNTRL and ARM_RD_CNTRL functions
 PARAMETERS  : None.
 RETURN VALUE: None.
 LIMITATIONS : None.
----------------------------------------------------------------------------- */
#define ARM9_RESET_S_BIT \
{ \
   int tmp; \
   \
   tmp = ARM_RD_CNTRL(); \
   tmp &= ~S_bit; \
   ARM_WR_CNTRL(tmp); \
}