rif.h

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 151 行

//=====================================================================  
//      TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION             
// Property of Texas Instruments -- For Unrestricted Internal Use Only   
// Unauthorized reproduction and/or distribution is strictly prohibited  
// This product is protected under copyright law and trade secret law as 
// an unpublished work.Created 2001,(C) Copyright 2001 Texas Instruments.
// All rights reserved.                                                  
//=====================================================================  

#ifndef RIF_H
#define RIF_H

//---------------------------------------------------------
//NAME        : <LIB_function_name>
//DESCRIPTION : 
//PARAMETERS  : 
//RETURN VALUE: 
//LIMITATIONS :
//---------------------------------------------------------
#include "global_types.h"
#include "mem.h"
#include "error.h"
#include "result.h"

#define MEM_DSP_RIF_ADDR        0xE1013800

#define RIF_ADDR_ARM    MEM_DSP_RIF_ADDR


#define RIF_ADDR_T              0x0000 

#define RIF_ADDR_R              (0x0001<<1)


#define RIF_SPCX_OFFSET         (0x02<<1)            /* SPCX */


#define RIF_CTRL_MCM            0x0001          /* MCM*/
#define RIF_CTRL_XRST           0x0002          /*XRST */
#define RIF_CTRL_XRDY           0x0004          /*XRDY*/
#define RIF_CTRL_CLKX_AUTO      0x0008          /* CLOCK AUTO */
#define RIF_CTRL_TXM            0x0010          /*TXM*/
#define RIF_CTRL_NCLK_EN        0x0020          /* CLOCK EXT*/
#define RIF_CTRL_NCLK13_EN      0x0040          /* CLOCK13 */
#define RIF_CTRL_AL_EM          0x0080          /*ALMOST EMPTY */
#define RIF_CTRL_FIFOET         0x0100          /*FIFO EMPTY*/
#define RIF_CTRL_FIFOFT         0x0200          /*FIFO FULL*/
#define RIF_CTRL_THRET          0x0400          /*THRESHOLD 10 12*/
#define RIF_CTRL_PTV            0x2000          /* PTV CLOCK DIVISION*/

#define RIF_SPCX_MCM_POS          0
#define RIF_SPCX_XRST_POS         1
#define RIF_SPCX_XRDY_POS         2
#define RIF_SPCX_CLKX_AUTO_POS    3
#define RIF_SPCX_TXM_POS          4
#define RIF_SPCX_NCLK_EN_POS      5
#define RIF_SPCX_NCK13_EN_POS     6
#define RIF_SPCX_ALMOST_EMPTY_POS 7
#define RIF_SPCX_FIFO_EMPTY_POS   8
#define RIF_SPCX_FIFO_FULL_POS    9
#define RIF_SPCX_THRESHOLD_POS    10
#define RIF_SPCX_DIV_CLK_POS      12


#define RIF_SPCR_OFFSET         (0x03<<1)    /*SPCR RECEIVE */


#define RIF_CTRL_DLB            0x0001          /* DLB */
#define RIF_CTRL_RRST           0x0002          /* RRST */
#define RIF_CTRL_RRDY           0x0004          /* RRDY */
#define RIF_CTRL_RSRFULL        0x0008          /* RSRFULL */
#define RIF_CTRL_AL_FU          0x0010          /* ALMOST FULL */
#define RIF_CTRL_FIFOER         0x0020          /*FIFO EMPTY */
#define RIF_CTRL_FIFOFR         0x0040          /* FIFO FULL*/          
#define RIF_CTRL_THRER          0x0080          /* THRESHOLD*/

#define RIF_SPCR_DLB_POS          0
#define RIF_SPCR_RRST_POS         1
#define RIF_SPCR_RRDY_POS         2
#define RIF_SPCR_RSRFULL_POS      3
#define RIF_SPCR_ALMOST_FULL_POS  4
#define RIF_SPCR_FIFO_EMPTY_POS   5
#define RIF_SPCR_FIFO_FULL_POS    6
#define RIF_SPCR_THRESHOLD_POS    7
#define RIF_SPCR_XINT_MASK_POS    10
#define RIF_SPCR_RINT_MASK_POS    11
#define RIF_SPCR_XDMA_MASK_POS    12
#define RIF_SPCR_RDMA_MASK_POS    13
#define RIF_SPCR_CLKLB_POS        14


#define RIF_CTRL_FIRST          0x0001          /* first bit */
#define RIF_CTRL_RSTAT          0x0070          /* R FIFO STATUS */
#define RIF_CTRL_RFOUR          0x0050          /* FOUR WORD in R FIFO  */
#define RIF_CTRL_RTWO           0x0010          /* TWO word in R FIFO */

#define MAP_RIF_ADDR_T_DSP      REG16(RIF_ADDR_ARM + RIF_ADDR_T)
#define MAP_RIF_ADDR_R_DSP      REG16(RIF_ADDR_ARM + RIF_ADDR_R)
#define MAP_RIF_SPCX_REG_DSP    REG16(RIF_ADDR_ARM + RIF_SPCX_OFFSET)
#define MAP_RIF_SPCR_REG_DSP    REG16(RIF_ADDR_ARM + RIF_SPCR_OFFSET)


#define RIF_SPCX_RES_VAL	0x059E				/* SPCX reset value */
#define RIF_SPCX_RD_MASK	0x7FFF				/* SPCX read mask */
#define RIF_SPCX_RW_MASK	0x7C7B				/* SPCX read/write mask */

#define RIF_SPCR_RES_VAL	0x3CA2				/* SPCR reset value */
#define RIF_SPCR_RD_MASK	0x7FFF				/* SPCR read mask */
#define RIF_SPCR_RW_MASK	0x7F83				/* SPCR read/write mask */


/* ----- Prototypes ----- */

void RIF_InitSpcx(int Mcm, int Xrst, int Clk_auto, int Txm, int Nclk_en, int Nclk13_en, int Threshold, int Ptv);

void RIF_InitSpcr(int Dlb, int Rrst, int Threshold, int Xint, int Rint, int Xdma, int Rdma, int Clklb);

void RIF_BclkInternalLoopback(int Clk_loop);

int RIF_GetMcm(void);
int RIF_GetXrst(void);
int RIF_GetClkauto(void);
int RIF_GetTxm(void);
int RIF_GetNclken(void);
int RIF_GetNclk13(void);
int RIF_GetThresholdx(void);
int RIF_GetPtv(void);
int RIF_GetFifoet(void);
int RIF_GetFifoft(void);
void RIF_GetSpcx(int *Mcm, int *Xrst,
                      int *Clk_auto, int *Txm,
                      int *Nclk_en,int *Nclk13_en,
                      int *Threshold,int *Ptv );
int RIF_GetDlb(void);
int RIF_GetRrst(void);
int RIF_GetThresholdx(void);
void RIF_GetSpcr(int *Dlb, int *Rrst,
                      int *Threshold);
void RIF_Reset(void);
int RIF_GetFifoafr(void);
int RIF_GetFifoer(void);
int RIF_TestRifReg(void);

void RIF_TestResetValue(void);
void RIF_TestWriteRead(void);

void RIF_EnableInternalClock(void);

#endif