📄 arm.h
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extern void ARM_FLUSH_ICACHE (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_FLUSH_ICACHE_ENTRY -
DESCRIPTION : Flush I_Cache Entry -
PARAMETERS : See ARM925 CP15 Register 7 specification: Virtual Address -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_FLUSH_ICACHE_ENTRY (int);
/*
-----------------------------------------------------------------------------
NAME : ARM_FLUSH_DCACHE -
DESCRIPTION : Flush D_Cache -
PARAMETERS : See ARM925 CP15 Register 7 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_FLUSH_DCACHE (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_FLUSH_DCACHE_ENTRY -
DESCRIPTION : Flush D_Cache Entry -
PARAMETERS : See ARM925 CP15 Register 7 specification: Virtual Address -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_FLUSH_DCACHE_ENTRY (int);
/*
-----------------------------------------------------------------------------
NAME : ARM_CLEAN_DCACHE -
DESCRIPTION : Clean D_Cache -
PARAMETERS : See ARM925 CP15 Register 7 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_CLEAN_DCACHE (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_CLEAN_DCACHE_ENTRY -
DESCRIPTION : Clean D_Cache Entry -
PARAMETERS : See ARM925 CP15 Register 7 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_CLEAN_DCACHE_ENTRY (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_CLEAN_FLUSH_DCACHE_ENTRY -
DESCRIPTION : Clean and Flush D_Cache Entry -
PARAMETERS : See ARM925 CP15 Register 7 specification: Virtual Address -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_CLEAN_FLUSH_DCACHE_ENTRY (int);
/*
-----------------------------------------------------------------------------
NAME : ARM_FLUSH_TLB -
DESCRIPTION : Invalidate all entries in TLB (I_TLB and D_TLB) -
PARAMETERS : See ARM925 CP15 Register 8 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_FLUSH_TLB (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_Section -
DESCRIPTION : Build 1st level descriptor and address of this descriptor -
Write this descriptor into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, access permission bit-
domain used, Cacheable and Bufferable bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_Section(PA, VA, TTB, ap, domain, CB ) \
{ \
int add_D1, val_D1; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((PA & 0xFFF00000) | (ap << 10) | (domain << 5) |(CB << 2) | 0x2); \
\
*(UWORD32*)add_D1 = val_D1; \
}
/*
------------------------------------------------------------------------------
NAME : ARM_LargePage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_LargePage(PA, VA, TTB, page_base,\
ap0, ap1, ap2, ap3, domain, CB) \
{ \
int add_D1, val_D1; \
int add_D2, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFFC00) | (domain << 5) | 0x1); \
\
add_D2 = ((page_base & 0xFFFFFC00) | (((VA & 0x000FF000) >> 12) << 2)); \
val_D2 = ((PA & 0xFFFF0000) | (ap3 << 10) | (ap2 << 8) | (ap1 << 6) |\
(ap0 << 4) | (CB << 2) | 0x1);\
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
/*
------------------------------------------------------------------------------
NAME : ARM_SmallPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_SmallPage(PA, VA, TTB, page_base, \
ap0, ap1, ap2, ap3, domain, CB) \
{ \
int add_D1, val_D1; \
int add_D2, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFFC00) | (domain << 5) | 0x1); \
\
add_D2 = ((page_base & 0xFFFFFC00) | (((VA & 0x000FF000) >> 12) << 2)); \
val_D2 = ((PA & 0xFFFFF000) | (ap3 << 10) | (ap2 << 8) | (ap1 << 6) |\
(ap0 << 4) | (CB << 2) | 0x2); \
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
/*
------------------------------------------------------------------------------
NAME : ARM_TinyPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : Physical Address, Virtual Address, TTB, page table base, -
access permission bits, domain used, C_mmu and B_mmu bits -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_TinyPage(PA, VA, TTB, page_base, ap, domain, CB) \
{ \
int add_D1, add_D2; \
int val_D1, val_D2; \
\
add_D1 = ((TTB & 0xFFFFC000) | (((VA >> 20) << 2) & 0x00003FFF)); \
val_D1 = ((page_base & 0xFFFFF000) | (domain << 5) | 0x3); \
\
add_D2 = ((page_base & 0xFFFFF000) | (((VA & 0x000FFC00) >> 10) << 2)); \
val_D2 = ((PA & 0xFFFFFC00) | (ap << 4) | (CB << 2) | 0x3); \
\
*(UWORD32*)add_D1 = val_D1; \
*(UWORD32*)add_D2 = val_D2; \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_SET_REG15_CONFIGURATION -
DESCRIPTION : Write value into CP15 register15 (Configuration Register) -
PARAMETERS : See ARM925 CP15 Register 15 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_SET_REG15_CONFIGURATION (UWORD32);
/*
------------------------------------------------------------------------------
NAME : ARM_SET_WINCE_MODE -
DESCRIPTION : Reset OS Bit (bit 5) -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_SET_WINCE_MODE() \
{ \
UWORD32 tmp_value = ARM_READ_REG15_CONFIGURATION(); \
\
tmp_value = (tmp_value & (~O_bit)); \
\
ARM_SET_REG15_CONFIGURATION(tmp_value); \
}
/*
------------------------------------------------------------------------------
NAME : ARM_SET_ARM915T_MODE -
DESCRIPTION : Set OS Bit (bit 5) -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_SET_ARM915T_MODE() \
{ \
UWORD32 tmp_value = ARM_READ_REG15_CONFIGURATION(); \
\
tmp_value = (tmp_value | O_bit); \
\
ARM_SET_REG15_CONFIGURATION(tmp_value); \
}
/*
------------------------------------------------------------------------------
NAME : ARM_READ_REG15_C0 -
DESCRIPTION : Read Reg15, c0 of CP15 -
PARAMETERS : None. -
RETURN VALUE: read value -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
extern UWORD32 ARM_READ_REG15_C0(void);
/*
------------------------------------------------------------------------------
NAME : ARM_WRITE_REG15_C0 -
DESCRIPTION : Read Reg15, c0 of CP15 -
PARAMETERS : None. -
RETURN VALUE: read value -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
extern void ARM_WRITE_REG15_C0(UWORD32);
/*
------------------------------------------------------------------------------
NAME : ARM_DISABLE_PREFETCH -
DESCRIPTION : Set bit 16 of REG15, c0 -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
------------------------------------------------------------------------------
*/
#define ARM_DISABLE_PREFETCH \
{ \
UWORD32 tmp_value = ARM_READ_REG15_C0(); \
\
tmp_value = (tmp_value | prefetch_bit); \
\
ARM_WRITE_REG15_C0(tmp_value); \
}
#endif
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