📄 arm.h
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/*
===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : ARM.h
//
// Description : Header file for the ARM functions
//
// Project : Satustar
//
// Author : Sebastien Sabatier
// FUNCTIONS PROVIDED :
//
// CP15 Register1: Control register
//
// ARM_READ_REG1 (external function)
// ARM_WRITE_REG1 (external function)
// ARM_MMU_ON
// ARM_MMU_OFF
// ARM_MMU_OFF_ONLY
// ARM_SET_ALIGNMENT_BIT
// ARM_WBUFFER_ON
// ARM_WBUFFER_OFF
// ARM_SET_BIG_ENDIAN
// ARM_SET_LITTLE_ENDIAN
// ARM_SET_S_BIT
// ARM_RESET_S_BIT
// ARM_SET_R_BIT
// ARM_RESET_R_BIT
// ARM_DCACHE_ON
// ARM_ICACHE_ON
// ARM_DCACHE_OFF
// ARM_ICACHE_OFF
//
// CP15 Register2: Translation Table Base Register
//
// ARM_READ_TTBR (external function)
// ARM_WRITE_TTBR (external function)
//
// CP15 Register3: Domain Access Control Register
//
// ARM_READ_DOMAIN_REG (external function)
// ARM_WRITE_DOMAIN_REG (external function)
//
// CP15 Register5: Fault Status Register
//
// ARM_READ_FSR (external function)
//
// CP15 Register6: Fault Address Register
//
// ARM_READ_FAR (external function)
//
// CP15 Register7: Cache Functions
//
// ARM_FLUSH_CACHE (external function)
// ARM_FLUSH_ICACHE (external function)
// ARM_FLUSH_ICACHE_ENTRY (external function)
// ARM_FLUSH_DCACHE (external function)
// ARM_FLUSH_DCACHE_ENTRY (external function)
// ARM_CLEAN_DCACHE (external function)
// ARM_CLEAN_DCACHE_ENTRY (external function)
// ARM_CLEAN_FLUSH_DCACHE_ENTRY (external function)
//
// CP15 Register8: TLB Functions
//
// FLUSH_TLB (external function)
//
// CP15 Register15: TI Operations
//
// ARM_SET_REG15_CONFIGURATION (external function)
// ARM_SET_WINCE_MODE
// ARM_SET_ARM915T_MODE
// ARM_DISABLE_PREFETCH
//
// TRANSLATION TABLE MACROS PROVIDED:
//
// ARM_Section
// ARM_LargePage
// ARM_SmallPage
// ARM_TinyPage
//
===============================================================================
*/
#ifndef _ARM__HH
#define _ARM__HH
#include "top.h"
/* Constants used to identify bits in the CP15 Reg1 Control Reg */
#define M_bit 0x1 /* Enable Address translation & page access */
#define A_bit 0x2 /* Alignment fault enable/disable */
#define C_bit 0x4 /* Data cache enable/disable */
#define W_bit 0x8 /* Write buffer enable/disable */
#define B_bit 0x80 /* Big(1)/Little(0) Endian configuration */
#define S_bit 0x100 /* System protection bit */
#define R_bit 0x200 /* ROM protection bit */
#define I_bit 0x1000 /* Instruction Cache enable/disable */
#define V_bit 0x2000 /* Alternate Vectors select bit */
/* Constants used to identify bits in CP15 Reg15 Configuration Register */
#define L_bit 0x01 /* Lock Enable */
#define T_bit 0x02 /* Transparent mode */
#define Cl_bit 0x04 /* D-Cache clean and flush entry mode */
#define Wb_bit 0x18 /* Write Buffer Configuration */
#define O_bit 0x20 /* OS Configuration: 0 -> WinCE, 1 -> arm915t mode */
#define St_bit 0x80 /* Instruction Cache streaming Disable */
#define prefetch_bit 0x10000 /* disable NC instruction Prefetching */
#define CACHEABLE 2
#define BUFFERABLE 1
/* Access Permissions - not shifted into position */
#define NO_ACCESS 0
#define SVC_R 0
#define SVC_RW 1
#define NO_USR_W 2
#define ALL_ACCESS 3
#define DOMAIN0 0
#define DOMAIN1 1
#define DOMAIN2 2
#define DOMAIN3 3
#define DOMAIN4 4
#define DOMAIN5 5
#define DOMAIN6 6
#define DOMAIN7 7
#define DOMAIN8 8
#define DOMAIN9 9
#define DOMAIN10 10
#define DOMAIN11 11
#define DOMAIN12 12
#define DOMAIN13 13
#define DOMAIN14 14
#define DOMAIN15 15
/*
-----------------------------------------------------------------------------
NAME : ARM_WRITE_REG1 -
DESCRIPTION : Write value into CP15 register1 (used to enable or disable -
MMU, Instruction Cache, Write Buffer, Data Cache, ... -
PARAMETERS : See ARM925 CP15 Register 1 specification -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern void ARM_WRITE_REG1 (int value);
/*
-----------------------------------------------------------------------------
NAME : ARM_READ_REG1 -
DESCRIPTION : Read value from CP15 register1 (used to enable or disable -
MMU, Instruction Cache, Write Buffer, Data Cache, ... -
PARAMETERS : See ARM925 CP15 Register 1 specification -
RETURN VALUE: value of CP15 register1 (contained in register R0) -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
extern int ARM_READ_REG1 (void);
/*
-----------------------------------------------------------------------------
NAME : ARM_MMU_ON -
DESCRIPTION : Enable MMU of ARM925 using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_MMU_ON \
{ \
int tmp; \
\
tmp = ARM_READ_REG1(); \
tmp |= M_bit; \
ARM_WRITE_REG1(tmp); \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_MMU_OFF -
DESCRIPTION : Disable MMU, WB and Data Cache of ARM925 using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_MMU_OFF \
{ \
int tmp; \
\
ARM_WRITE_BUFFER_OFF; \
ARM_DCACHE_OFF; \
tmp = ARM_READ_REG1(); \
tmp &= ~M_bit; \
ARM_WRITE_REG1(tmp); \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_MMU_OFF_ONLY -
DESCRIPTION : Only switch off MMU of ARM925 using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_MMU_OFF_ONLY \
{ \
int tmp; \
\
tmp = ARM_READ_REG1(); \
tmp &= ~M_bit; \
ARM_WRITE_REG1(int tmp); \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_SET_ALIGNMENT_BIT -
DESCRIPTION : Set Alignment bit using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_SET_ALIGNMENT_BIT \
{ \
int tmp; \
\
tmp = ARM_READ_REG1(); \
tmp |= A_bit; \
ARM_WRITE_REG1(tmp); \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_WRITE_BUFFER_ON -
DESCRIPTION : Enable Write Buffer using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_WRITE_BUFFER_ON \
{ \
int tmp; \
\
tmp = ARM_READ_REG1(); \
tmp |= W_bit; \
ARM_WRITE_REG1(tmp); \
}
/*
-----------------------------------------------------------------------------
NAME : ARM_WRITE_BUFFER_OFF -
DESCRIPTION : Disable Write Buffer using -
ARM_WRITE_REG1 and ARM_READ_REG1 functions -
PARAMETERS : None. -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define ARM_WRITE_BUFFER_OFF \
{ \
int tmp; \
\
tmp = ARM_READ_REG1(); \
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