wcdma_rci.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2001, (C) Copyright 2001 Texas Instruments. All rights reserved
//
//========================================================================
#include "wcdma_mapping.h"
#ifndef _wcdma_rci__H
#define _wcdma_rci__H
//Standard Register offset list
#define MULTI_MODE_CTL_0_OFFSET 0x1200
#define MULTI_MODE_CTL_1_OFFSET 0x12A0
#define MULTI_IMMED_CTL_0_OFFSET 0x1201
#define MULTI_IMMED_CTL_1_OFFSET 0x1202
#define MULTI_IMMED_CTL_2_OFFSET 0x1203
#define MULTI_IMMED_CTL_3_OFFSET 0x1204
#define MULTI_IMMED_CTL_4_OFFSET 0x1205
#define MULTI_IMMED_CTL_5_OFFSET 0x1206
#define MULTI_GCC_0_CTL_0_OFFSET 0x1210
#define MULTI_GCC_0_CTL_1_OFFSET 0x1230
#define MULTI_GCC_0_CTL_2_OFFSET 0x1250
#define MULTI_GCC_1_CTL_0_OFFSET 0x1211
#define MULTI_GCC_1_CTL_1_OFFSET 0x1231
#define MULTI_GCC_1_CTL_2_OFFSET 0x1251
#define MULTI_GCC_2_CTL_0_OFFSET 0x1212
#define MULTI_GCC_2_CTL_1_OFFSET 0x1232
#define MULTI_GCC_2_CTL_2_OFFSET 0x1252
#define MULTI_GCC_3_CTL_0_OFFSET 0x1213
#define MULTI_GCC_3_CTL_1_OFFSET 0x1233
#define MULTI_GCC_3_CTL_2_OFFSET 0x1253
#define MULTI_GCC_4_CTL_0_OFFSET 0x1214
#define MULTI_GCC_4_CTL_1_OFFSET 0x1234
#define MULTI_GCC_4_CTL_2_OFFSET 0x1254
#define MULTI_GCC_5_CTL_0_OFFSET 0x1215
#define MULTI_GCC_5_CTL_1_OFFSET 0x1235
#define MULTI_GCC_5_CTL_2_OFFSET 0x1255
#define MULTI_GCC_6_CTL_0_OFFSET 0x1216
#define MULTI_GCC_6_CTL_1_OFFSET 0x1236
#define MULTI_GCC_6_CTL_2_OFFSET 0x1256
#define MULTI_GCC_7_CTL_0_OFFSET 0x1217
#define MULTI_GCC_7_CTL_1_OFFSET 0x1237
#define MULTI_GCC_7_CTL_2_OFFSET 0x1257
#define MULTI_GCC_8_CTL_0_OFFSET 0x1218
#define MULTI_GCC_8_CTL_1_OFFSET 0x1238
#define MULTI_GCC_8_CTL_2_OFFSET 0x1258
#define MULTI_GCC_9_CTL_0_OFFSET 0x1219
#define MULTI_GCC_9_CTL_1_OFFSET 0x1239
#define MULTI_GCC_9_CTL_2_OFFSET 0x1259
#define MULTI_GCC_10_CTL_0_OFFSET 0x121a
#define MULTI_GCC_10_CTL_1_OFFSET 0x123a
#define MULTI_GCC_10_CTL_2_OFFSET 0x125a
#define MULTI_GCC_11_CTL_0_OFFSET 0x121b
#define MULTI_GCC_11_CTL_1_OFFSET 0x123b
#define MULTI_GCC_11_CTL_2_OFFSET 0x125b
#define MULTI_GCC_12_CTL_0_OFFSET 0x121c
#define MULTI_GCC_12_CTL_1_OFFSET 0x123c
#define MULTI_GCC_12_CTL_2_OFFSET 0x125c
#define MULTI_GCC_13_CTL_0_OFFSET 0x121d
#define MULTI_GCC_13_CTL_1_OFFSET 0x123d
#define MULTI_GCC_13_CTL_2_OFFSET 0x125d
#define MULTI_GCC_14_CTL_0_OFFSET 0x121e
#define MULTI_GCC_14_CTL_1_OFFSET 0x123e
#define MULTI_GCC_14_CTL_2_OFFSET 0x125e
#define MULTI_GCC_15_CTL_0_OFFSET 0x121f
#define MULTI_GCC_15_CTL_1_OFFSET 0x123f
#define MULTI_GCC_15_CTL_2_OFFSET 0x125f
#define MULTI_GCC_16_CTL_0_OFFSET 0x1220
#define MULTI_GCC_16_CTL_1_OFFSET 0x1240
#define MULTI_GCC_16_CTL_2_OFFSET 0x1260
#define MULTI_GCC_17_CTL_0_OFFSET 0x1221
#define MULTI_GCC_17_CTL_1_OFFSET 0x1241
#define MULTI_GCC_17_CTL_2_OFFSET 0x1261
#define MULTI_GCC_18_CTL_0_OFFSET 0x1222
#define MULTI_GCC_18_CTL_1_OFFSET 0x1242
#define MULTI_GCC_18_CTL_2_OFFSET 0x1262
#define MULTI_GCC_19_CTL_0_OFFSET 0x1223
#define MULTI_GCC_19_CTL_1_OFFSET 0x1243
#define MULTI_GCC_19_CTL_2_OFFSET 0x1263
#define MULTI_GCC_20_CTL_0_OFFSET 0x1224
#define MULTI_GCC_20_CTL_1_OFFSET 0x1244
#define MULTI_GCC_20_CTL_2_OFFSET 0x1264
#define MULTI_GCC_21_CTL_0_OFFSET 0x1225
#define MULTI_GCC_21_CTL_1_OFFSET 0x1245
#define MULTI_GCC_21_CTL_2_OFFSET 0x1265
#define MULTI_GCC_22_CTL_0_OFFSET 0x1226
#define MULTI_GCC_22_CTL_1_OFFSET 0x1246
#define MULTI_GCC_22_CTL_2_OFFSET 0x1266
#define MULTI_GCC_23_CTL_0_OFFSET 0x1227
#define MULTI_GCC_23_CTL_1_OFFSET 0x1247
#define MULTI_GCC_23_CTL_2_OFFSET 0x1267
#define SPI_CS_CTL_OFFSET 0x1270
#define GCC_OFFSET_OFFSET 0x1271
#define MULTI_INT_STAT_OFFSET 0x1272
#define MULTI_INT_CLR_OFFSET 0x1273
#define MULTI_IMMED_CTL_OFFSET 0x1274
#define CHIPSX4_TO_WAIT_OFFSET 0x1275
#define SYNC_GPIO_0_CTL_0_OFFSET 0x1280
#define SYNC_GPIO_0_CTL_1_OFFSET 0x1288
#define SYNC_GPIO_1_CTL_0_OFFSET 0x1281
#define SYNC_GPIO_1_CTL_1_OFFSET 0x1289
#define SYNC_GPIO_2_CTL_0_OFFSET 0x1282
#define SYNC_GPIO_2_CTL_1_OFFSET 0x128a
#define SYNC_GPIO_3_CTL_0_OFFSET 0x1283
#define SYNC_GPIO_3_CTL_1_OFFSET 0x128b
#define SYNC_GPIO_4_CTL_0_OFFSET 0x1284
#define SYNC_GPIO_4_CTL_1_OFFSET 0x128c
#define SYNC_GPIO_5_CTL_0_OFFSET 0x1285
#define SYNC_GPIO_5_CTL_1_OFFSET 0x128d
#define SYNC_GPIO_6_CTL_0_OFFSET 0x1286
#define SYNC_GPIO_6_CTL_1_OFFSET 0x128e
#define SYNC_GPIO_7_CTL_0_OFFSET 0x1287
#define SYNC_GPIO_7_CTL_1_OFFSET 0x128f
#define SYNC_GPIO_MISSED_STAT_OFFSET 0x1290
#define SYNC_GPIO_IMMED_CTL_OFFSET 0x1291
#define GPIO_ALT_HW_CTL_A_OFFSET 0x1100
#define GPIO_ALT_HW_CTL_B_OFFSET 0x1101
#define GPIO_ALT_HW_CTL_C_OFFSET 0x1102
#define GPIO_ALT_HW_CTL_D_OFFSET 0x1103
#define GPIO_VALUE_A_OFFSET 0x1120
#define GPIO_VALUE_B_OFFSET 0x1121
#define GPIO_VALUE_C_OFFSET 0x1122
#define GPIO_VALUE_D_OFFSET 0x1123
#define TX_OUTPUT_MODE_CDMA_OFFSET 0x1005
#define RX_FIFO_CTL_OFFSET 0x1011
//MULTI_MODE_CTL_0
//-------------------------
#define MULTI_MODE_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_MODE_CTL_0_OFFSET) << 2))
#define MULTI_MODE_CTL_0_RES_VAL 0x40000000
//R/W
//-------------------------
//MULTI_MODE_CTL_1
//-------------------------
#define MULTI_MODE_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_MODE_CTL_1_OFFSET) << 2))
#define MULTI_MODE_CTL_1_RES_VAL 0x00000001
//R/W
//-------------------------
//MULTI_IMMED_CTL_0
//-------------------------
#define MULTI_IMMED_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_0_OFFSET) << 2))
#define MULTI_IMMED_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_IMMED_CTL_1
//-------------------------
#define MULTI_IMMED_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_1_OFFSET) << 2))
#define MULTI_IMMED_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_IMMED_CTL_2
//-------------------------
#define MULTI_IMMED_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_2_OFFSET) << 2))
#define MULTI_IMMED_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_IMMED_CTL_3
//-------------------------
#define MULTI_IMMED_CTL_3 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_3_OFFSET) << 2))
#define MULTI_IMMED_CTL_3_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_IMMED_CTL_4
//-------------------------
#define MULTI_IMMED_CTL_4 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_4_OFFSET) << 2))
#define MULTI_IMMED_CTL_4_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_IMMED_CTL_5
//-------------------------
#define MULTI_IMMED_CTL_5 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_IMMED_CTL_5_OFFSET) << 2))
#define MULTI_IMMED_CTL_5_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_0_CTL_0
//-------------------------
#define MULTI_GCC_0_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_0_CTL_0_OFFSET) << 2))
#define MULTI_GCC_0_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_0_CTL_1
//-------------------------
#define MULTI_GCC_0_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_0_CTL_1_OFFSET) << 2))
#define MULTI_GCC_0_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_0_CTL_2
//-------------------------
#define MULTI_GCC_0_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_0_CTL_2_OFFSET) << 2))
#define MULTI_GCC_0_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_1_CTL_0
//-------------------------
#define MULTI_GCC_1_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_1_CTL_0_OFFSET) << 2))
#define MULTI_GCC_1_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_1_CTL_1
//-------------------------
#define MULTI_GCC_1_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_1_CTL_1_OFFSET) << 2))
#define MULTI_GCC_1_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_1_CTL_2
//-------------------------
#define MULTI_GCC_1_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_1_CTL_2_OFFSET) << 2))
#define MULTI_GCC_1_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_2_CTL_0
//-------------------------
#define MULTI_GCC_2_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_2_CTL_0_OFFSET) << 2))
#define MULTI_GCC_2_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_2_CTL_1
//-------------------------
#define MULTI_GCC_2_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_2_CTL_1_OFFSET) << 2))
#define MULTI_GCC_2_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_2_CTL_2
//-------------------------
#define MULTI_GCC_2_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_2_CTL_2_OFFSET) << 2))
#define MULTI_GCC_2_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_3_CTL_0
//-------------------------
#define MULTI_GCC_3_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_3_CTL_0_OFFSET) << 2))
#define MULTI_GCC_3_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_3_CTL_1
//-------------------------
#define MULTI_GCC_3_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_3_CTL_1_OFFSET) << 2))
#define MULTI_GCC_3_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_3_CTL_2
//-------------------------
#define MULTI_GCC_3_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_3_CTL_2_OFFSET) << 2))
#define MULTI_GCC_3_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_4_CTL_0
//-------------------------
#define MULTI_GCC_4_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_4_CTL_0_OFFSET) << 2))
#define MULTI_GCC_4_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_4_CTL_1
//-------------------------
#define MULTI_GCC_4_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_4_CTL_1_OFFSET) << 2))
#define MULTI_GCC_4_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_4_CTL_2
//-------------------------
#define MULTI_GCC_4_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_4_CTL_2_OFFSET) << 2))
#define MULTI_GCC_4_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_5_CTL_0
//-------------------------
#define MULTI_GCC_5_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_5_CTL_0_OFFSET) << 2))
#define MULTI_GCC_5_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_5_CTL_1
//-------------------------
#define MULTI_GCC_5_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_5_CTL_1_OFFSET) << 2))
#define MULTI_GCC_5_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_5_CTL_2
//-------------------------
#define MULTI_GCC_5_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_5_CTL_2_OFFSET) << 2))
#define MULTI_GCC_5_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_6_CTL_0
//-------------------------
#define MULTI_GCC_6_CTL_0 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_6_CTL_0_OFFSET) << 2))
#define MULTI_GCC_6_CTL_0_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_6_CTL_1
//-------------------------
#define MULTI_GCC_6_CTL_1 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_6_CTL_1_OFFSET) << 2))
#define MULTI_GCC_6_CTL_1_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_6_CTL_2
//-------------------------
#define MULTI_GCC_6_CTL_2 REG32(WCDMA_CS_LB+((WCDMA_RCI_BASE_ADDR+MULTI_GCC_6_CTL_2_OFFSET) << 2))
#define MULTI_GCC_6_CTL_2_RES_VAL 0x00000000
//R/W
//-------------------------
//MULTI_GCC_7_CTL_0
//-------------------------
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