mpui.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 337 行
H
337 行
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :omap_32_apif.h
//
// Date of Module Modification:5/2/02
// Date of Generation :5/3/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _MPUI_INTERFACE__H
#define _MPUI_INTERFACE__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define MPUI_INTERFACE_CTRL_REG_OFFSET 0x00
#define MPUI_INTERFACE_DEBUG_ADDR_OFFSET 0x04
#define MPUI_INTERFACE_DEBUG_DATA_OFFSET 0x08
#define MPUI_INTERFACE_DEBUG_FLAG_OFFSET 0x0C
#define MPUI_INTERFACE_STATUS_REG_OFFSET 0x10
#define MPUI_INTERFACE_DSP_STATUS_REG_OFFSET 0x14
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_OFFSET 0x18
#define MPUI_INTERFACE_DSP_API_CONFIG_OFFSET 0x1C
#define MPUI_INTERFACE_DSP_MISC_CFG_OFFSET 0x20
#define MPUI_INTERFACE_ENHANCED_CNTL_REG_OFFSET 0x24
//MPUI_INTERFACE_CTRL_REG
//-------------------
#define MPUI_INTERFACE_CTRL_REG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_CTRL_REG_OFFSET)
//R
#define MPUI_INTERFACE_CTRL_REG_WORD_SWAP_CTRL_POS 21
#define MPUI_INTERFACE_CTRL_REG_WORD_SWAP_CTRL_NUMB 2
#define MPUI_INTERFACE_CTRL_REG_WORD_SWAP_CTRL_RES_VAL 0x0
//R/W
#define MPUI_INTERFACE_CTRL_REG_ACCESS_PRIORITY_POS 18
#define MPUI_INTERFACE_CTRL_REG_ACCESS_PRIORITY_NUMB 3
#define MPUI_INTERFACE_CTRL_REG_ACCESS_PRIORITY_RES_VAL 0x000
//R/W
#define MPUI_INTERFACE_CTRL_REG_ENDIANISM_POS 16
#define MPUI_INTERFACE_CTRL_REG_ENDIANISM_NUMB 2
#define MPUI_INTERFACE_CTRL_REG_ENDIANISM_RES_VAL 0x11
//R/W
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_POS 8
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_NUMB 8
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_RES_VAL 0xFF
//R/W
#define MPUI_INTERFACE_CTRL_REG_ACCESS_FACTOR_POS 4
#define MPUI_INTERFACE_CTRL_REG_ACCESS_FACTOR_NUMB 4
#define MPUI_INTERFACE_CTRL_REG_ACCESS_FACTOR_RES_VAL 0x1
//R/W
#define MPUI_INTERFACE_CTRL_REG_API_ERR_EN_POS 3
#define MPUI_INTERFACE_CTRL_REG_API_ERR_EN_NUMB 1
#define MPUI_INTERFACE_CTRL_REG_API_ERR_EN_RES_VAL 0x1
//R/W
//R/W
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_EN_POS 1
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_EN_NUMB 1
#define MPUI_INTERFACE_CTRL_REG_TIMEOUT_EN_RES_VAL 0x1
//R/W
//R/W
//MPUI_INTERFACE_DEBUG_ADDR
//-------------------
#define MPUI_INTERFACE_DEBUG_ADDR REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DEBUG_ADDR_OFFSET)
//R
#define MPUI_INTERFACE_DEBUG_ADDR_ADR_SAV_POS 0
#define MPUI_INTERFACE_DEBUG_ADDR_ADR_SAV_NUMB 24
#define MPUI_INTERFACE_DEBUG_ADDR_ADR_SAV_RES_VAL 0xFFFFFF
//R
//MPUI_INTERFACE_DEBUG_DATA
//-------------------
#define MPUI_INTERFACE_DEBUG_DATA REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DEBUG_DATA_OFFSET)
#define MPUI_INTERFACE_DEBUG_DATA_DATA_SAV_POS 0
#define MPUI_INTERFACE_DEBUG_DATA_DATA_SAV_NUMB 32
#define MPUI_INTERFACE_DEBUG_DATA_DATA_SAV_RES_VAL 0xFFFFFFFF
//R
//MPUI_INTERFACE_DEBUG_FLAG
//-------------------
#define MPUI_INTERFACE_DEBUG_FLAG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DEBUG_FLAG_OFFSET)
//R/W
#define MPUI_INTERFACE_DEBUG_FLAG_HOST_ID_POS 13
#define MPUI_INTERFACE_DEBUG_FLAG_HOST_ID_NUMB 2
#define MPUI_INTERFACE_DEBUG_FLAG_HOST_ID_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_SMOD_SAV_POS 11
#define MPUI_INTERFACE_DEBUG_FLAG_SMOD_SAV_NUMB 2
#define MPUI_INTERFACE_DEBUG_FLAG_SMOD_SAV_RES_VAL 0x11
//R
#define MPUI_INTERFACE_DEBUG_FLAG_CS_SAV_POS 9
#define MPUI_INTERFACE_DEBUG_FLAG_CS_SAV_NUMB 2
#define MPUI_INTERFACE_DEBUG_FLAG_CS_SAV_RES_VAL 0x00
//R
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_SAV_POS 6
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_SAV_NUMB 3
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_SAV_RES_VAL 0x000
//R
#define MPUI_INTERFACE_DEBUG_FLAG_RNW_SAV_POS 5
#define MPUI_INTERFACE_DEBUG_FLAG_RNW_SAV_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_RNW_SAV_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_BYTE_SAV_POS 4
#define MPUI_INTERFACE_DEBUG_FLAG_BYTE_SAV_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_BYTE_SAV_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_ERR_POS 3
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_ERR_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_BURST_SIZE_ERR_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_TIMEOUT_ERR_POS 2
#define MPUI_INTERFACE_DEBUG_FLAG_TIMEOUT_ERR_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_TIMEOUT_ERR_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_API_ERR_POS 1
#define MPUI_INTERFACE_DEBUG_FLAG_API_ERR_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_API_ERR_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DEBUG_FLAG_ABORT_FLAG_POS 0
#define MPUI_INTERFACE_DEBUG_FLAG_ABORT_FLAG_NUMB 1
#define MPUI_INTERFACE_DEBUG_FLAG_ABORT_FLAG_RES_VAL 0x0
//R
//MPUI_INTERFACE_STATUS_REG
//-------------------
#define MPUI_INTERFACE_STATUS_REG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_STATUS_REG_OFFSET)
//R
#define MPUI_INTERFACE_STATUS_REG_ACCESS_STATUS_POS 11
#define MPUI_INTERFACE_STATUS_REG_ACCESS_STATUS_NUMB 2
#define MPUI_INTERFACE_STATUS_REG_ACCESS_STATUS_RES_VAL 0x11
//R
#define MPUI_INTERFACE_STATUS_REG_TIMEOUT_VAL_POS 3
#define MPUI_INTERFACE_STATUS_REG_TIMEOUT_VAL_NUMB 8
#define MPUI_INTERFACE_STATUS_REG_TIMEOUT_VAL_RES_VAL 0xFF
//R
#define MPUI_INTERFACE_STATUS_REG_CS_EN_POS 2
#define MPUI_INTERFACE_STATUS_REG_CS_EN_NUMB 1
#define MPUI_INTERFACE_STATUS_REG_CS_EN_RES_VAL 0x1
//R
#define MPUI_INTERFACE_STATUS_REG_ACCESS_DONE_POS 1
#define MPUI_INTERFACE_STATUS_REG_ACCESS_DONE_NUMB 1
#define MPUI_INTERFACE_STATUS_REG_ACCESS_DONE_RES_VAL 0x1
//R
#define MPUI_INTERFACE_STATUS_REG_HOMNSAM_FLAG_POS 0
#define MPUI_INTERFACE_STATUS_REG_HOMNSAM_FLAG_NUMB 1
#define MPUI_INTERFACE_STATUS_REG_HOMNSAM_FLAG_RES_VAL 0x1
//R
//MPUI_INTERFACE_DSP_STATUS_REG
//-------------------
#define MPUI_INTERFACE_DSP_STATUS_REG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DSP_STATUS_REG_OFFSET)
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_HRHOMNSAM_POS 11
#define MPUI_INTERFACE_DSP_STATUS_REG_HRHOMNSAM_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_HRHOMNSAM_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_HAHOMNSAM_POS 10
#define MPUI_INTERFACE_DSP_STATUS_REG_HAHOMNSAM_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_HAHOMNSAM_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_PENRESETDPLL_POS 9
#define MPUI_INTERFACE_DSP_STATUS_REG_PENRESETDPLL_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_PENRESETDPLL_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE7_POS 8
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE7_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE7_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE6_POS 7
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE6_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLE6_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEDPLL_POS 6
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEDPLL_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEDPLL_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEPERIPH_POS 5
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEPERIPH_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_PEIDLEPERIPH_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUIACK_POS 4
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUIACK_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUIACK_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUAVIS_POS 3
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUAVIS_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUAVIS_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUXF_POS 2
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUXF_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_CPUXF_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_MCU_POS 1
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_MCU_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_MCU_RES_VAL 0x0
//R
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_POS 0
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_NUMB 1
#define MPUI_INTERFACE_DSP_STATUS_REG_RESET_RES_VAL 0x0
//R
//MPUI_INTERFACE_DSP_BOOT_CONFIG
//-------------------
#define MPUI_INTERFACE_DSP_BOOT_CONFIG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DSP_BOOT_CONFIG_OFFSET)
//R/W
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR2_POS 10
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR2_NUMB 6
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR2_RES_VAL 0x0
//R/W
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR1_POS 4
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR1_NUMB 6
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_BOOT_RHEA_PTR1_RES_VAL 0x0
//R/W
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_DSP_BOOT_MODE_POS 0
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_DSP_BOOT_MODE_NUMB 4
#define MPUI_INTERFACE_DSP_BOOT_CONFIG_DSP_BOOT_MODE_RES_VAL 0x0
//R/W
//MPUI_INTERFACE_DSP_API_CONFIG
//-------------------
#define MPUI_INTERFACE_DSP_API_CONFIG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DSP_API_CONFIG_OFFSET)
//R/W
#define MPUI_INTERFACE_DSP_API_CONFIG_API_SIZE_POS 0
#define MPUI_INTERFACE_DSP_API_CONFIG_API_SIZE_NUMB 16
#define MPUI_INTERFACE_DSP_API_CONFIG_API_SIZE_RES_VAL 0xFFFF
//R/W
//MPUI_INTERFACE_DSP_MISC_CFG
//-------------------
#define MPUI_INTERFACE_DSP_MISC_CFG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_DSP_MISC_CFG_OFFSET)
//R/W
#define MPUI_INTERFACE_DSP_MISC_CFG_CPUBION_POS 8
#define MPUI_INTERFACE_DSP_MISC_CFG_CPUBION_NUMB 1
#define MPUI_INTERFACE_DSP_MISC_CFG_CPUBION_RES_VAL 0x0
//R/W
//R/W
//MPUI_INTERFACE_ENHANCED_CNTL_REG
//-------------------
#define MPUI_INTERFACE_ENHANCED_CNTL_REG REG32(MPUI_INTERFACE_BASE_ADDR_ARM+MPUI_INTERFACE_ENHANCED_CNTL_REG_OFFSET)
//R
#define MPUI_INTERFACE_ENHANCED_CNTL_REG_DPS_EN_POS 0
#define MPUI_INTERFACE_ENHANCED_CNTL_REG_DPS_EN_NUMB 1
#define MPUI_INTERFACE_ENHANCED_CNTL_REG_DPS_EN_RES_VAL 0x0
//R/W
#endif
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?