eac.h
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//=========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments (TI) -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work. Created 1987,(C) Copyright 1997-2002 TI.
// All rights reserved.
//=========================================================================
//
// Filename : eac.h
//
// Description : Header file for EAC (Enhanced Audio Controller)
//
// Project : Perseus2
//
// Author : Patrick SAUVIGNET p-sauvignet@ti.com
//==========================================================================
#ifndef EAC_H_INCLUDED
#define EAC_H_INCLUDED
#include "global_types.h"
#include "mapping.h"
#include "errorcodes.h"
#include "testaccess.h"
#include "reset.h"
#include "result.h"
//========================================================================
// [1]
// Generated from Perseus2 registers database
// under filename : perseus2_uart_modem_irda.h
//
// Date of Module Modification: 2002-04-07
// Date of Generation: 2002-09-19
//========================================================================
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define EAC_CPCFR1_OFFSET 0x00
#define EAC_CPCFR2_OFFSET 0x02
#define EAC_CPCFR3_OFFSET 0x04
#define EAC_CPCFR4_OFFSET 0x06
#define EAC_CPTCTL_OFFSET 0x08
#define EAC_CPTTADR_OFFSET 0x0A
#define EAC_CPTDATL_OFFSET 0x0C
#define EAC_CPTDATH_OFFSET 0x0E
#define EAC_CPTVSLL_OFFSET 0x10
#define EAC_CPTVSLH_OFFSET 0x12
#define EAC_MPCTR_OFFSET 0x20
#define EAC_MPMCCFR_OFFSET 0X22
#define EAC_MPACCFR_OFFSET 0x24
#define EAC_MPADLTR_OFFSET 0x26
#define EAC_MPADMTR_OFFSET 0x28
#define EAC_MPADLRR_OFFSET 0x2A
#define EAC_MPADMRR_OFFSET 0x2C
#define EAC_BPCTR_OFFSET 0x30
#define EAC_BPMCCFR_OFFSET 0X32
#define EAC_BPACCFR_OFFSET 0x34
#define EAC_BPADLTR_OFFSET 0x36
#define EAC_BPADMTR_OFFSET 0x38
#define EAC_BPADLRR_OFFSET 0x3A
#define EAC_BPADMRR_OFFSET 0x3C
#define EAC_AMSCFR_OFFSET 0x40
#define EAC_AMVCTR_OFFSET 0x42
#define EAC_AM1VCTR_OFFSET 0x44
#define EAC_AM2VCTR_OFFSET 0x46
#define EAC_AM3VCTR_OFFSET 0x48
#define EAC_ASTCTR_OFFSET 0x4A
#define EAC_APD1LCR_OFFSET 0x4C
#define EAC_APD1RCR_OFFSET 0x4E
#define EAC_APD2LCR_OFFSET 0x50
#define EAC_APD2RCR_OFFSET 0x52
#define EAC_APD3LCR_OFFSET 0x54
#define EAC_APD3RCR_OFFSET 0x56
#define EAC_APD4R_OFFSET 0x58
#define EAC_ADWDR_OFFSET 0x5A
#define EAC_ADRDR_OFFSET 0x5C
#define EAC_AGCFR_OFFSET 0x5E
#define EAC_AGCTR_OFFSET 0x60
//EAC_CPCFR1
//-------------------
#define EAC_CPCFR1 REG16(EAC_BASE_ADDR_ARM+EAC_CPCFR1_OFFSET)
#define EAC_CPCFR1_RESERVED_POS 8
#define EAC_CPCFR1_RESERVED_NUMB 8
#define EAC_CPCFR1_RESERVED_RES_VAL 0X00
//R
#define EAC_CPCFR1_MTSL_POS 3
#define EAC_CPCFR1_MTSL_NUMB 5
#define EAC_CPCFR1_MTSL_RES_VAL 0X1
//R/W
#define EAC_CPCFR1_MODE_POS 0
#define EAC_CPCFR1_MODE_NUMB 3
#define EAC_CPCFR1_MODE_RES_VAL 0X4
//R/W
//EAC_CPCFR2
//-------------------
#define EAC_CPCFR2 REG16(EAC_BASE_ADDR_ARM+EAC_CPCFR2_OFFSET)
#define EAC_CPCFR2_RESERVED_POS 8
#define EAC_CPCFR2_RESERVED_NUMB 8
#define EAC_CPCFR2_RESERVED_RES_VAL 0X00
//R
#define EAC_CPCFR2_TSLOL_POS 6
#define EAC_CPCFR2_TSLOL_NUMB 2
#define EAC_CPCFR2_TSLOL_RES_VAL 0X0
//R/W
#define EAC_CPCFR2_BPTSL_POS 3
#define EAC_CPCFR2_BPTSL_NUMB 3
#define EAC_CPCFR2_BPTSL_RES_VAL 0X01
//R/W
#define EAC_CPCFR2_TSLL_POS 0
#define EAC_CPCFR2_TSLL_NUMB 3
#define EAC_CPCFR2_TSLL_RES_VAL 0X1
//R/W
//EAC_CPCFR3
//-------------------
#define EAC_CPCFR3 REG16(EAC_BASE_ADDR_ARM+EAC_CPCFR3_OFFSET)
#define EAC_CPCFR3_RESERVED_POS 8
#define EAC_CPCFR3_RESERVED_NUMB 8
#define EAC_CPCFR3_RESERVED_RES_VAL 0X00
//R
#define EAC_CPCFR3_DDLY_POS 7
#define EAC_CPCFR3_DDLY_NUMB 1
#define EAC_CPCFR3_DDLY_RES_VAL 0X1
//R/W
#define EAC_CPCFR3_TRSEN_POS 6
#define EAC_CPCFR3_TRSEN_NUMB 1
#define EAC_CPCFR3_TRSEN_RES_VAL 0X0
//R/W
#define EAC_CPCFR3_CLKBP_POS 5
#define EAC_CPCFR3_CLKBP_NUMB 1
#define EAC_CPCFR3_CLKBP_RES_VAL 0X1
//R/W
#define EAC_CPCFR3_CSYNCP_POS 4
#define EAC_CPCFR3_CSYNCP_NUMB 1
#define EAC_CPCFR3_CSYNCP_RES_VAL 0X0
//R/W
#define EAC_CPCFR3_CSYNCL_POS 3
#define EAC_CPCFR3_CSYNCL_NUMB 1
#define EAC_CPCFR3_CSYNCL_RES_VAL 0X1
//R/W
#define EAC_CPCFR3_RESERVED2_POS 2
#define EAC_CPCFR3_RESERVED2_NUMB 1
#define EAC_CPCFR3_RESERVED2_RES_VAL 0X0
//R/W
#define EAC_CPCFR3_CSCLKD_POS 1
#define EAC_CPCFR3_CSCLKD_NUMB 1
#define EAC_CPCFR3_CSCLKD_RES_VAL 0X1
//R/W
#define EAC_CPCFR3_CSYNCD_POS 0
#define EAC_CPCFR3_CSYNCD_NUMB 1
#define EAC_CPCFR3_CSYNCD_RES_VAL 0X1
//R/W
//EAC_CPCFR4
//-------------------
#define EAC_CPCFR4 REG16(EAC_BASE_ADDR_ARM+EAC_CPCFR4_OFFSET)
#define EAC_CPCFR4_RESERVED_POS 8
#define EAC_CPCFR4_RESERVED_NUMB 8
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