rheaswitch.h

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 380 行 · 第 1/2 页

#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ITPEND_ERR_POS                                                         2
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ITPEND_ERR_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ITPEND_ERR_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_DMAREQ_ERR_POS                                                         1
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_DMAREQ_ERR_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_DMAREQ_ERR_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ERR_NIRQ_POS                                                           0
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ERR_NIRQ_NUMB                                                          1
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_ERR_NIRQ_RES_VAL                                                       0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_TSP
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_TSP                                                                           REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_TSP_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_TSP_DSP_PERIPH_LOCK_POS                                                         1
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_DSP_PERIPH_LOCK_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_DSP_PERIPH_LOCK_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_TSP_ARM_PERIPH_LOCK_POS                                                         0
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_ARM_PERIPH_LOCK_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_ARM_PERIPH_LOCK_RES_VAL                                                     0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_TSP
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_TSP                                                                           REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_TSP_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_BOTH_LCK_ERR_POS                                                       3
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_BOTH_LCK_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_BOTH_LCK_ERR_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ITPEND_ERR_POS                                                         2
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ITPEND_ERR_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ITPEND_ERR_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_DMAREQ_ERR_POS                                                         1
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_DMAREQ_ERR_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_DMAREQ_ERR_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ERR_NIRQ_POS                                                           0
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ERR_NIRQ_NUMB                                                          1
#define            RHSW_ARM_RHSW_ARM_STA_TSP_RHSW_ERR_NIRQ_RES_VAL                                                       0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_GEA3
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3                                                                          REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_GEA3_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_DSP_PERIPH_LOCK_POS                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_DSP_PERIPH_LOCK_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_DSP_PERIPH_LOCK_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_ARM_PERIPH_LOCK_POS                                                        0
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_ARM_PERIPH_LOCK_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_ARM_PERIPH_LOCK_RES_VAL                                                    0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_GEA3
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_GEA3                                                                          REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_GEA3_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_BOTH_LCK_ERR_POS                                                      3
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_BOTH_LCK_ERR_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_BOTH_LCK_ERR_RES_VAL                                                  0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ITPEND_ERR_POS                                                        2
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ITPEND_ERR_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ITPEND_ERR_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_DMAREQ_ERR_POS                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_DMAREQ_ERR_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_DMAREQ_ERR_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ERR_NIRQ_POS                                                          0
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ERR_NIRQ_NUMB                                                         1
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_RHSW_ERR_NIRQ_RES_VAL                                                      0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_USIM
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_USIM                                                                          REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_USIM_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_USIM_DSP_PERIPH_LOCK_POS                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_DSP_PERIPH_LOCK_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_DSP_PERIPH_LOCK_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_USIM_ARM_PERIPH_LOCK_POS                                                        0
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_ARM_PERIPH_LOCK_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_ARM_PERIPH_LOCK_RES_VAL                                                    0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_USIM
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_USIM                                                                          REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_USIM_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_BOTH_LCK_ERR_POS                                                      3
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_BOTH_LCK_ERR_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_BOTH_LCK_ERR_RES_VAL                                                  0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ITPEND_ERR_POS                                                        2
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ITPEND_ERR_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ITPEND_ERR_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_DMAREQ_ERR_POS                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_DMAREQ_ERR_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_DMAREQ_ERR_RES_VAL                                                    0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ERR_NIRQ_POS                                                          0
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ERR_NIRQ_NUMB                                                         1
#define            RHSW_ARM_RHSW_ARM_STA_USIM_RHSW_ERR_NIRQ_RES_VAL                                                      0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_CIPHER
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER                                                                        REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_CIPHER_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_DSP_PERIPH_LOCK_POS                                                      1
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_DSP_PERIPH_LOCK_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_DSP_PERIPH_LOCK_RES_VAL                                                  0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_ARM_PERIPH_LOCK_POS                                                      0
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_ARM_PERIPH_LOCK_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_ARM_PERIPH_LOCK_RES_VAL                                                  0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_CIPHER
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER                                                                        REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_CIPHER_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_BOTH_LCK_ERR_POS                                                    3
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_BOTH_LCK_ERR_NUMB                                                   1
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_BOTH_LCK_ERR_RES_VAL                                                0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ITPEND_ERR_POS                                                      2
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ITPEND_ERR_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ITPEND_ERR_RES_VAL                                                  0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_DMAREQ_ERR_POS                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_DMAREQ_ERR_NUMB                                                     1
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_DMAREQ_ERR_RES_VAL                                                  0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ERR_NIRQ_POS                                                        0
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ERR_NIRQ_NUMB                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_RHSW_ERR_NIRQ_RES_VAL                                                    0x1
//R/W

#endif